MIPS32™ 4KE™ Processor Cores Software User`s Manual

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3 Turning Off PDtrace™ Trace Trace is turned off when the following expression evaluates true: ( (TraceControlTS and (not TraceControlOn))) and ((not TraceControlTS) and (not TCBCONTROLAOn)) ) or ( (not MatchEnable) (not TriggerEnable) 224 and and MIPS32™ 4KE™ Processor Cores Software User’s Manual, Revision 02. Also read the data corresponding to the byte index into the DataLo register Yes 2#010 I, D Index Store Tag Index Update the SPRAM tag at the specified index from the TagLo Coprocessor 0 register. 00 Copyright © 2000-2002 MIPS Technologies Inc. This avoids bubbles being injected into the pipeline on branch instructions. The second multiply operation (Mult2) enters the E stage. 00 Copyright © 2000-2002 MIPS Technologies Inc. 1 CP0 Register Summary Table 5-1 lists the CP0 registers in numerical order. If TMS is sampled LOW on the rising edge of TCK, the controller transitions to the Capture_IR state. 161 Chapter 7 Caches 162 MIPS32™ 4KE™ Processor Cores Software User’s Manual, Revision 02. 00 Copyright © 2000-2002 MIPS Technologies Inc. MIPS32™ 4KE™ Processor Cores Software User’s Manual, Revision 02. SYNC Synchronize Shared Memory 31 26 25 SYNC 21 20 SPECIAL 16 15 11 10 6 0 5 0 SYNC stype 000000 00 0000 0000 0000 0 6 15 001111 5 6 Format: SYNC (stype = 0 implied) MIPS32 Purpose: To order loads and stores. If the pipeline restarts as the result of an enabled interrupt, that interrupt is taken between the WAIT instruction and the following instruction (EPC for the interrupt points at the instruction following the WAIT instruction). Generally, the cache policy for these programmable regions is defined by a cacheability attribute field associated with that region of memory. A UDI instruction can operate on any one or two general-purpose registers or immediate data contained within the instruction, and must always write the result of each instruction back to a general purpose register. The only addressing mode that load and store instructions directly support is base register plus 16-bit signed immediate offset. 4 A Stage: Align During the Align stage: • A separate aligner aligns loaded data with its word boundary. Figure 2-5 on page 15 shows a timing diagram of a data cache miss. 1 Instruction Bit Encoding Table 12-2 through Table 12-9 describe the encoding used for the MIPS16 ASE. Table 4-6 gives the offsets from the vector base address as a function of the exception