AK5397EQ

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1u 1 + 910 R216 AINRP 2 R243 C252 100p BIASR1 C225 220u 3 4 VOP- NC NC -IN V+ +IN OUT 8 7 V- NC 6 R220 R222 5. It is possible to connect AKM’s D/A converter evaluation boards and the digital-amplifier through the BNC connector. *In case of using external clock (MCLK) through a BNC connector (J400), short R423(EXT) and R422 by 0ohm resistance, and open R421 (XTL). (8) SW400 ( Toggle switch ) Toggle type-switch PDN for AK5397. Crosstalk <KM120900> 2015/06 - 25- [AKD5397-SB] REVISION HISTORY Date (YY/MM/DD) 15/06/01 Manual Revision KM120900 Board Revision 0 Reason Page First edition - <KM120900> Contents 2015/06 - 26- [AKD5397-SB] IMPORTANT NOTICE 0. TDM Mode setting for AK5397 <KM120900> 2015/06 - 8- [AKD5397-SB] [4] Clock / Data format settings (1) Settings of Clocks (BICK, LRCK) Clock speed settings of BICK, LRCK can be set change by switching CLK1, CLK2. BICK fs MCLK R431 R432 R433 R434 (MCLK/8) (MCLK/4) (MCLK/2) (MCLK/1) 32fs 64fs 64fs 128fs 128fs 256fs 256fs 512fs 32fs 64fs 64fs 128fs 128fs 256fs 256fs 512fs 512fs = 24. ) (11) J203,J202 ( Analog data ) BNC Connector : Single-ended Analog Input. FFT (-1dBFS Input) AK5397 FFT ( -60dBFS Input) AVDD=5. (5) PORT1 ( pin header ) Pin header for evaluation (MCLK, BICK, LRCK). 3V (Regulator) ・Input Frequency ・Measurement Frequency : 1kHz : 20 ~ 20kHz @48kHz / 20～40kHz @96kHz / 20～80kHz @192kHz ・Temperature : Room [Measurement Results] 1. (2-2-3) Input/Output digital data from PORT2 (DATA) *The A/D converted data is output from SDTO1, SDTO2 of PORT2 (DATA). 0V/VSS, MCLK=128fs, fin=1kHz +0 -10 -20 -30 -40 -50 -60 -70 d B F S -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 20 50 100 200 500 1k 2k 5k 10k 20k 50k 80k Hz Figure 22. 033u VSS A A Title Size A3 - 295 4 3 Date: 2 AKD5397-SB Document Number Rev 0 Analog Input Thursday, March 12, 2015 Sheet 1 2 of 5 5 4 DVDD1 3 2 1 VCC1 U2 U300A 3 DIF D OVF 4 SDTO2_VD 5 6 7 SDTO1_VD DIT1 8 DIT0 9 10 1 2 11 12 -> B 1 A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 A8 B8 VCCA VCCB DIR VCCB GND GND OE GND C300 DIF_VC 21 LED300 1 2 R300 20 19 1k VSS 2 SDTO2_VCPR4353K V1 U1 TRANS DIF2 24 23 17 PDN_VCB 3 MCLK_VC 4 SDTI_4103 5 BICK_4103 6 LRCK_4103 7 SDTO1_VC 16 DIT1_VC 15 DIT0_VC PDN DIF1 MCLK DIF0 SDTI TXP BICK TXN 22 J300 BNC_TX 14 20 R301 240 24 19 150 22 13 LRCK VSS 18 C306 C307 4 5 BICK_VD 6 7 8 9 10 1 M_SN 8 2 11 12 <-> B A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 A8 B8 VCCA VCCB DIR VCCB GND OE GND GND C302 9 21 LRCK_VC FS0/CSN VDD FS1/CDTI CKS1 FS2/CCLK CKS0 FS3/CDTO BLS C1 ANS 19 BICK_VC 11 17 4 TDMIN2_VD 5 6 TDMIN1_VD 7 8 MCLK_VD 9 10 PDN1 1 2 11 12 12 15 VSS DIT0_VC 14 13 14 24 AK4103A VSS 23 22 13 HPFE CKS0 CKS1 CKS2 B DVDD2 A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 A8 B8 VCCA VCCB DIR VCCB GND OE GND GND 21 SW300 20 TDMIN2_VC RP300 19 18 TDMIN1_VC 17 16 HPFE CKS0 CKS1 CKS2 DIT0 DIT1 1 2 3 4 5 6 7 8 9 MCLK_VC HPFE 1 CKS0 2 CKS1 3 CKS2 4 DIT0 5 DIT1 6 7 8 16 15 14 13 12 11 10 9 SW DIP-8 15 10k 14 PDN_VCA MONO TDM0 TDM1 M_SN DIF SDFIL SDM1 SDM2 VSS 24 23 22 DVDD2 13 RP301 SW301 1 2 3 4 5 6 7 8 9 C305 74LVC8T245 0. Linearity <KM120900> 2015/06 - 24- [AKD5397-SB] fs = 192 kHz AK5397 Frequency Response AVDD=5. Keep “H” when AK4103A is in use; keep “L” when AK4103A is not in use. 1u AVSS 37 AVDD 39 VCOM 40 41 AVDD 42 AVSS 43 TOUT R108 0 RIN+ 9 PDN LIN- RIN- TEST1 TEST2 BVSS BVSS HPFE MONO CKS0 TDM1 CKS1 TDM0 CKS2 TDMIN2 33 RIN_P0 PDN TDMIN1 0. Ordering guide AKD5397-SB Evaluation board for AK5397 FUNCTION DIT with BNC digital output BNC connector for an external clock input -7V +7V -VOP +VOP Regulators 3. 1u C513 47u + R512 0 R502 0 DVDD1 DVDD2 VSS A A Title Size A3 - 325 4 3 Date: 2 AKD5397-SB Document Number Rev Power Supply Thursday, March 12, 2015 Sheet 1 5 0 of 5 . Mode 0 1 2 3 4 5 6 7 8 9 10 11 12 Normal TDM1 L TDM0 L M/SN DIF L L H L H L H L H L H L H N/A (Slave) H (Master) L TDM256 L H (Slave) H (Master) L TDM128 H H (Slave) H (Master) N/A H L N/A SDTO 32bit, MSB justified 32bit, I2S Compatible 32bit, MSB justified 32bit, I2S Compatible 32bit, MSB justified 32bit, I2S Compatible 32bit, MSB justified 32bit, I2S Compatible 32bit, MSB justified 32bit, I2S Compatible 32bit, MSB justified 32bit, I2S Compatible N/A LRCK I/O H/L L/H H/L L/H ↑ ↓ ↑ ↓ ↑ ↓ ↑ ↓ N/A I I O O I I O O I I O O N/A BICK I/O Default I Table 3-1 I O O 256fs I 256fs I 256fs 256fs 128fs 128fs 128fs 128fs N/A O O I I O O N/A Table 9