HIGH CMR, VERY HIGH SPEED OPTICALLY COUPLED ISOLATOR LOGIC GATE OUTPUT 6N13

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Greenville Ave, Suite 240, Allen, TX 75002 USA Tel: (214) 495-0755 Fax: (214) 495-0901 e-mail [email protected] http://www. 01µF ceramic disc capacitor adjacent to each isolator. 5V level on the Low to High of the output voltage pulse. APPLICATIONS l Line receiver, data transmission l Computer-peripheral interface l Data multiplexing l Pulse transformer replacement OPTION SM OPTION G 7. 6 The tEHL enable input propagation delay is measured from the 1. 5V level on the Low to High transition of the enable input voltage pulse to the 1. E91231 DESCRIPTION The 6N137 / ICPL2601 optocouplers consist of a GaAsP light emitting diode and a high gain integrated photo detector to provide 2500Volts RMS electrical isolation between input and output. The power supply bus for the isolator(s) should be seperate from the bus for any active loads. This unique design provides maximum ac and dc circuit isolation while achieving TTL compatibility. 8V) 10 No external pull up is required for a high logic state on the enable input. 5V level on the Low to High transition of the output voltage pulse. 75 mA level Low to High transition of the input current pulse to the 1. 5mA Unless otherwise noted ) PARAMETER Propagation Delay Time to Logic Low at Output ( fig 1 )( note4 ) SYM DEVICE MIN TYP MAX UNITS TEST CONDITION tPHL 55 75 ns RL = 350Ω, CL = 15pF Propagation Delay Time to Logic High at Output ( fig 1 )( note5 ) tPLH 45 75 ns RL = 350Ω, CL = 15pF Propagation Delay Time of Enable from VEH to VEL ( note6 ) tEHL 14 ns RL = 350Ω, CL = 15pF VEL = 0V, VEH = 3V Propagation Delay Time of Enable from VEL to VEH ( note7 ) tELH 25 ns RL = 350Ω, CL = 15pF VEL = 0V, VEH = 3V Common Mode Transient Immunity at Logic High Level Output ( fig 2 )( note8 ) CMH 6N137 ICPL2601 10000 1000 10000 V/µs V/µs IF = 0mA, VCM = 50VPP RL= 350Ω,VOH= 2Vmin. equal to or less than 50%, t = 1min, TA= 25°C µA R. 7 The tELH enable input propagation delay is measured from the 1. 5V level on the High to Low of the output voltage pulse. 5V level on the High to Low transition of the output voltage pulse. 1 SWITCHING TEST CIRCUIT IF PULSE GENERATOR ZO = 50Ω tr = 5ns 0 VO 5V 1. 9 CML is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state (ie Vout < 0. 75mA level High to Low transition of the input current pulse to the 1