There are many types of substrates used in electronic devices whose thickness should be uniform. The thickness uniformity of silicon substrates used for largescale integrated circuits (LSIs) should be less than the depth of focus of the exposure equipment. The numerical aperture (NA) of exposure equipment is expected to increase as the size of transistors in LSIs decreases, which will result in the requirement of more uniform thickness. According to the International Technology Roadmap for Semiconductors (ITRS) 2011 (International Technology Roadmap for Semiconductors 2011), the site front least-square range (SFQR) specified for each year is less than half of the dynamic random access memory (DRAM) half pitch, for example, it is expected to be less than 13 nm in 2020.
Silicon-on-insulator (SOI) substrates are used for high-performance LSIs. An SOI substrate has a very thin single-crystal silicon layer on a thin buried oxide (BOX) layer formed on a silicon substrate. The thickness uniformity of the silicon layer directly affects the threshold voltage of each transistor in an LSI and should be within ± 5%. A thinner silicon layer will be required as the transistor size in LSIs becomes smaller, and a thickness uniformity of less than ± 0.35 nm will be required in 2020 according to ITRS 2011.
Moreover, the thickness uniformity of quartz substrates for quartz resonators used in computers or in mobile telecommunication devices is also very important because multiple resonators are fabricated on a single quartz wafer by a lithography process and the thickness of the wafer directly affects their resonance frequencies. The resonance frequency of a quartz crystal resonator is inversely proportional to the thickness of the quartz crystal wafer, and the tolerance of the thickness variation in commercial products is ±10 ppm. Therefore, the initial thickness of the quartz wafer must be uniform to reduce the time required to adjust the resonance frequency for individual resonators in the final trimming process.
Improving the surface integrity, i.e., reducing the roughness and subsurface damage, of semiconductor materials is also important for the fabrication of high-performance electronic devices. Silicon carbide (SiC) is a promising next generation semiconductor power device material for high-power and high-temperature applications owing to its excellent properties such as wide energy band gap, excellent thermal conductivity, high saturated electron drift velocity, and good chemical stability. To apply SiC as a material for high-performance electronic devices, an atomically smooth and damage-free surface is essential, but SiC is one of the most difficult-to-machine materials because of its hardness and chemical inertness. In the present machining process for SiC wafers, a crystal ingot grown by a modified Lely method is first sliced by a wire saw and then planarized by lapping. Because of the high hardness of SiC, diamond abrasives are generally used in the slicing and lapping processes. These mechanical removal processes inevitably introduce microscratches and subsurface damage to the workpiece surface, which deteriorate surface integrity.
To prepare SiC wafers with a smooth surface, chemical mechanical polishing (CMP) is now widely used as a finishing process for the surfaces of single-crystal SiC and/or GaN substrates. Zhou et al. proposed the process of colloidal silica polishing, which requires a concentrated colloidal silica slurry at temperatures higher than 55o C and a pH value higher than 10 (Zhou et al. 1997; Neslen et al. 2001). Surfaces finished by CMP have no subsurface damage, as evaluated by cross-sectional transmission electron microscopy (XTEM), and CMP leads to the formation of a high-integrity epitaxial growth layer in terms of surface morphology (Zhou et al. 1997; Neslen et al. 2001; Saddow et al. 2001). However, the material removal rate of CMP is very low (less than 0.5 μm/h); hence, a novel highly efficient finishing technique that will generate an atomically smooth surface without introducing subsurface damage is crucial for improving the quality of SiC wafers.
To satisfy these requirements, we have developed some ultraprecision fabrication techniques utilizing atmospheric-pressure plasma. In this chapter, the methodologies and experimental results of thickness correction and surface finishing for functional materials using the developed methods are described.