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鄭博倫 (Po-Lun Cheng)
鄭博倫 (Po-Lun Cheng)
Process development on high-k gate stack, spacer formation and SiGe growth for CMOS performance enhancement
Process development on high-k gate stack, spacer formation and SiGe growth for CMOS performance enhancement
高介電閘極層,間隙層構成,與矽鍺磊晶之製程研發以強化CMOS效能
高介電閘極層,間隙層構成,與矽鍺磊晶之製程研發以強化CMOS效能
In this work, gate stack formation for high-k materials, spacer process improvement and stress enhancement process before SiGe growth are proposed. The first two processes can improve the performance of pMOSFET and nMOSPET, and the third process can improve the pMOSFET performance.
In this work, gate stack formation for high-k materials, spacer process improvement and stress enhancement process before SiGe growth are proposed. The first two processes can improve the performance of pMOSFET and nMOSPET, and the third process can improve the pMOSFET performance.
In gate stack formation, one feasible process flow integrating high-k and metal gate to decrease Jg (gate leakage) and EOT (electrical oxide thickness) without further impacting mobility is proposed, where dual work function metal gate can be formed by the proposed flow.
In gate stack formation, one feasible process flow integrating high-k and metal gate to decrease Jg (gate leakage) and EOT (electrical oxide thickness) without further impacting mobility is proposed, where dual work function metal gate can be formed by the proposed flow.
For spacer process improvement, instead of using conventional silane-based nitride, disilane-based nitride is proposed to use on spacer here, since the disilane precursor is non-sensitive to temperature. The experimental results show the improvements on thickness uniformity by 68% and uniformity on Idsat variation by 9%. The throughput enhancement and thermal budget reduction are also achieved.
For spacer process improvement, instead of using conventional silane-based nitride, disilane-based nitride is proposed to use on spacer here, since the disilane precursor is non-sensitive to temperature. The experimental results show the improvements on thickness uniformity by 68% and uniformity on Idsat variation by 9%. The throughput enhancement and thermal budget reduction are also achieved.
In SiGe growth, an improved pre-treatment process is proposed by performing cyclical O3/DHF clean, low temperature HCl bake and Si seed growth prior to SiGe growth. Then the in-situ boron-doping SiGe is deposited with dislocation free. It is shown that hole mobility is enhanced around 2.4 times. Furthermore, combined effects from enhanced mobility provided by compressive local stress and in-situ boron doping to decrease contact resistance contribute the Ion gain enhancement around 32% for pMOSFET.
In SiGe growth, an improved pre-treatment process is proposed by performing cyclical O3/DHF clean, low temperature HCl bake and Si seed growth prior to SiGe growth. Then the in-situ boron-doping SiGe is deposited with dislocation free. It is shown that hole mobility is enhanced around 2.4 times. Furthermore, combined effects from enhanced mobility provided by compressive local stress and in-situ boron doping to decrease contact resistance contribute the Ion gain enhancement around 32% for pMOSFET.
[1] P.-L. Cheng, C.-I. Liao, H.-R. Wu, Y.-C. Chen, C.-C. Chien, C.-L. Yang, S.-F. Tzou, J. Tang, R. Kodali, L. Washington, Y. Cho, V.-C. Chang, T. Fu, and W. Hsu, "Effective surface treatments for selective epitaxial SiGe growth in locally strained pMOSFETs." Journal of Semiconductor Science and Technology 2007, 22, 140-143.
[1] P.-L. Cheng, C.-I. Liao, H.-R. Wu, Y.-C. Chen, C.-C. Chien, C.-L. Yang, S.-F. Tzou, J. Tang, R. Kodali, L. Washington, Y. Cho, V.-C. Chang, T. Fu, and W. Hsu, "Effective surface treatments for selective epitaxial SiGe growth in locally strained pMOSFETs." Journal of Semiconductor Science and Technology 2007, 22, 140-143.
[2] P.-L. Cheng, C.-I. Liao, C.-C. Chien, C.-L. Yang, S.-F. Ting, L.-S. Jeng, C.-T. Huang, O. Cheng, S.-F. Tzou, W. Hsu, "Effectiveness of Si thin buffer layer for selective SiGe epitaxial growth in recessed source and drain for pMOS." Materials Chemistry and Physics 2008, 107, 471-475.
[2] P.-L. Cheng, C.-I. Liao, C.-C. Chien, C.-L. Yang, S.-F. Ting, L.-S. Jeng, C.-T. Huang, O. Cheng, S.-F. Tzou, W. Hsu, "Effectiveness of Si thin buffer layer for selective SiGe epitaxial growth in recessed source and drain for pMOS." Materials Chemistry and Physics 2008, 107, 471-475.
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