[1] I2C or IIC (Inter-Integrated Circuit; pronounced as "eye-squared-see" or "eye-two-see"), is a synchronous, multi-master/multi-slave, single-ended, serial communication protocol and bus invented in 1980 by Philips Semiconductors (now NXP Semiconductors). It's widely used to attach lower-speed peripheral integrated circuits (ICs) to processors and microcontrollers in short-distance, intra-board communication.
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It's synchronous master-slave type because both the master and slave can both send and receive data. It's bidirectional and half-duplex (), as well as running at various speeds.
I2C only uses 2 wires: SDA (serial data) and SCL (serial clock)
Operations
Operations
Topology
Topology
[2] The basic I2C topology is depicted as below:
[2]
[2] A master slave connects to 2+ slave nodes via 2 lines SDA and SCL, which are each connected to a voltage through a pull-up resistor.
I2C nodes exchange the data over this shared bus in forms of frames.
Frames
Frames
[2] An I2C master claims the bus by means of a so-called start condition. It then sends the address of the slave it wants to communicate with and an indication as to whether it wishes to read data from or write data to the slave, which acknowledges its presence and its readiness, after which the data is transmitted and acknowledged. The communication is terminated by means of a stop condition.
[2]
Start condition
Start condition
[2] Both the SDA and SCL starts as high. The start condition occurs if a node first pulls SDA low, and then pulls SCL low. Pulling these lines down in this order is used to “claim the bus” and the node that claims the bus is now the master. This procedure stops other nodes from taking control of the bus and thereby reduces the risk of contention, i.e., 2 nodes trying to claim or use the bus at the same time. Once a node has seized the bus, that node also starts sending the clock signal, used by both the master and the slave.
Slave address
Slave address
[2] Right after the start condition is the slave address, which specifies which node 2:57 the master wants to communicate with. Each node on an I2C bus must have a unique, fixed address, which are often 7 bits long, with the most significant bit first. I2C also supports 10-bit addresses, but are rare.
Addresses may be hard-coded for each device, but the address is often partially configurable (customizable) via external address jumpers (wires).
hard coded: permanently set during the manufacturing process and can't be changed by user, often physically built into device's internal circuitry.
E.g., this board's addresses can be partially configured via 3 jumpers. To configure this address, both A2 and A0 (logic 1s) must be jumpered and A1 would be left open (logic 0).
ACK bit
ACK bit
and a read/write bit that defines the operation. Every byte sent is followed by an Acknowledge (ACK) bit, where the receiver pulls the line low to confirm reception, or high to indicate a Not Acknowledge (NACK). The master continues to send data bytes until it finishes the transaction, at which point it issues a Stop condition by allowing SCL and then SDA to return to the high idle state.
The performance and speed of an I2C bus are influenced by the physical properties of the system. The pull-up resistors are essential for returning the lines to a high state, but their resistance values represent a compromise; higher resistance limits speed due to slower signal rise times, while lower resistance improves speed but increases power consumption. Typical values for these resistors range from 1 to 10 kilo-ohms. While devices are categorized by their maximum supported speeds—such as Standard, Fast, High-speed, and Ultra-fast modes—the actual data rate on the bus is ultimately constrained by these resistor values and the overall capacitance of the bus circuitry.
[2] Timing relationship between SDA and SCL SDA won't change between the clock rising edge and falling edge. Data is always read during the middle of the clock pulse. And during data transmission, SDA only transitions if the SCL is low, which is necessary because SDA transitioning when SCL is high indicates a start/stop condition.
[2]
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References
References
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