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A D (data) Flip-flop is a flip-flop circuit storing one bit of digital data (0/1). Its core parts include a data input (D), a clock signal (CLK), and outputs (Q and Q̄).
[2] Fig. 1
A standard D flip-flop's schematic resembles a SR flip-flop's, except it also uses the D input that controls the S and R inputs, which aren't labeled in Fig. 1 as the D and CLK inputs are the prominent terminals. Fig. 2 shows this more details
[4] Fig. 2
[5] Fig. 3 An SR flip-flop circuit
[3] In an SR flip-flop, the S and R inputs are always complement of each other to output a valid state (opposite state of another) (Fig. 3).
A D flip-flop's works similarly, but uses an inverter from the S input to the R input (Fig. 1).
Unlike basic latches that continually react to inputs whenever enabled, a D Flip-Flop is edge-triggered, only updating its output the moment the clock signal transitions:
Active clock edge (rising/falling): If the clock transitions (often on rising edges), the flip-flop samples the current D input value and copies it directly to the output Q.
Hold state: Between clock edges, changes on the D input are fully ignored. The flip-flop holds its previous value on Q, retaining the stored bit til the next active clock pulse.
[1] Flip-flop - Wikipedia
[2] GeekforGeeks
[5] SR latch with both inputs at 0 - (ElectricalEngineering - StackOverflow)