Conference2020

105. Design and Analysis of DC/DC Boost Converter Using Vertical GaN Power Device

      Min Su Cho, Hye Jin Mun, Sang Ho Lee, Jin Park, Hee Dae An, Jaewon Jang, Jin-Hyuk Bae and In Man Kang

      The 18th International Nanotech Symposium & Nano-Convergence Expo (July, 2020)

104. Design of Capacitorless DRAM based on Silicon Nanotube Structure with Junctionless Dual-Gate Field-Effect Transistor

      Sang Ho Lee,  Min Su Cho, Hye Jin Mun, Jin Park, Hee Dae An, Jaewon Jang, Jin-Hyuk Bae and In Man Kang

      The 18th International Nanotech Symposium & Nano-Convergence Expo (July, 2020)

103. Design of capacitorless DRAM based on multi-nanowire channels for improvement of memory performances

      Jin Park,  Min Su Cho, Hye Jin Mun, Sang Ho Lee, Hee Dae An, Jaewon Jang, Jin-Hyuk Bae and In Man Kang

      The 18th International Nanotech Symposium & Nano-Convergence Expo (July, 2020)

102. Effect of the grain boundary in polycrystalline silicon-based source and drain regions in 1T-DRAM

      Hee Dae An,  Min Su Cho, Hye Jin Mun, Sang Ho Lee, Jin Park, Jaewon Jang, Jin-Hyuk Bae and In Man Kang

      The 18th International Nanotech Symposium & Nano-Convergence Expo (July, 2020)

101. Analysis of CMOS Logic Inverter Based on Polycrystalline Silicon Layer in Gate-All-Around Junctionless Field-Effect-Transistor. 

      Hye Jin Mun, Min Su Cho, Won Douk Jang, Jun Hyeok Jang, Sang Ho Lee, Jaewon Jang, Jin-Hyuk Bae, and In Man Kang 

      제27회 한국반도체학술대회 (February, 2020)

100. Design of Capacitorless DRAM Based on Ultra-Thin Polycrystalline Silicon Junctionless Field-Effect Transistor with Dual Gate

      Sang Ho Lee, Min Su Cho, Jun Hyeok Jung, Won Douk Jang, Hye Jin Mun , Jae Won Jang , Jin Hyeok Bae and In Man Kang

      제27회 한국반도체학술대회 (February, 2020)