Unit 6.n - Verilog

Learning about Verilog & System Verilog

This is a Module about learning how to learn and use the hardware language Verilog.  I'll be posting my lessons, presentations, labs and other resources.  This is primarily a Resource Page, so that means it's a Mish-Mash of Silicon Wafer process content.  

I'm a huge supporter of Open Source and Creative Commons resources.  This is another way of saying Free, Equitable and Accessible resources...  

Construction Zone:

Author: Jim Burnham -  TopClown@STEAMClown.org.  License: Distributed as Open Source. 

I'm still working on this Unit... This will be developed in Spring and Spring of 2024 and taught a little in Spring 2024, but really for the 2024-2025 school year... I hope... Link to time sheet

  • Unit: Digital Logic Fundamentals
  • Module: Verilog - Technology - Resources
  • This is a LEARNING Activity : Lesson / Lab

Overview, Introduction & Prerequisites:

Verilog & System Verilog  

Resource Key:

📰 Slides / 📽️ Video/YouTube / ✨ Resources /  🖼️ Tutorial / 📖 Reading Activity / 📝 Writing Activity / 📖 📝 Reading/Writing / 🛠️ LAB Activity / 🚀 Quiz /  🔎 Review / 🍕 Extra Credit / 🕸️ Web Links

Sid Bar for Teachers: This Module or lesson is how I teach in my class. Many of the lessons might be specific to my class, but you could probably adjust them for your class.  I'll try to make them a neutral as I can, so they can be used in any Mathematics, Physics, Computer Science, or any other Engineering / Technology class.  Let me know how I can make that better. I'll try to keep this unit current and relevant.  Please let me know if any resource links are broken or not accessible.  Use this email link to let me know what is broken @ TopClown@STEAMClown.org 

Sponsor Shout Out

I would like to thank <Your Company or Organization Here> for their generous support of my classroom and curriculum development.  <Your Company or Organization Here> has <Your value proposition, call to action, & related content and message> 


(If you would like to sponsor this presentation, please contact TopClown@STEAMClown.org )

Learning Objective:

Module Scope:
  • Introduction to Verilog
  • Introduction to Silicon layout and Chip design
Learning Targets:
  • Learn Verilog & System Verilog  
Prior Knowledge:
  • No prior knowledge expected - You be you!!! 
Resources & Materials Needed:
  • PC, Laptop or Other device to access the Mathematics web application
  • Each lesson will have specific items needed to complete the labs and tasks

Prerequisites:

Caution & Safety  Considerations:

Primer:  "Aaron, I can imagine no way in which this thing could be considered anywhere remotely close to safe. All I know is I spent six hours in there and I'm still alive... You still want to do it?"

Essential Questions:

Key Academic Vocabulary or Concepts:

Lesson Topic - Verilog & System Verilog:

Do You Need To Build A New Clean Linux Build?

If you need to build Linux...


Stuff before the Verilog Lessons

These are the lessons to scaffold student knowledge of the digital Logic topics like Transistors, Logic Gates and Logic systems: 

These links will be posted later (soon) 

Verilog - Let's Build A Chip:

Verilog Lessons

High School Learning Verilog Module:



Verilog - Introduction

In this lesson you will get an overview of Verilog language oal of OpenROAD

Lesson Resources:

Verilog - Tools and Project Installation & Build Steps

In this lesson you are going to learn the steps to create your first Open ROAD project.  You will learn the options to execute the following steps:

Lesson Resources:

Verilog - Pre-Built - Project Introduction

In this lesson you are going to explore the running of the pre-installed example designs.  You will validate the tools and projects are installed correctly and have the ability to run some verification scripts on a default build of the GCD (Greatest Common Divisor) design. You will learn the steps to create your first Open ROAD Design. Explore / Review the following project features:

Lesson Resources:

Verilog - Your First Verilog Project - Building A Verilog Counter Design

In this lesson you are going to explore the creation of your first Verilog OpenROAD Project.  You will learn the steps to create your first Open ROAD Design. Explore / Review the following project features:

Lesson Resources:

Verilog - Virtual Studio Code - Project Introduction

Verilog - Verilog Synthesis


Lecture and Lab Topics:

Each lecture and lab modules will contain the following collateral and curriculum so that a STEAM teacher anywhere in a Highschool or Community College can implement the course work. 

Modules deliverables will include: (about 4 hours of 30 min Lectures & 8+ hours of Lab & Assessment activities) 

Working Topics - Move or Delete

links:

OpenROAD Introduction

Digital Logic - Introduction to the OpenROAD Project: This Module will cover the OpenROAD flows and Scripts

Modules deliverables will include: (about 4 hours of 30 min Lectures & 8+ hours of Lab & Assessment activities) 

Notes: This is a comment from @dralabeing that I need to follow up on, where to add some more timing analysis: Timing analysis is generally done at different stages- first time pre-layout after CTS, post-global-routing, after detailed routing and chip finishing. So this topic can be introduce sooner. 

Links & Resources:

Topics:

Links that will help us build this project:

Logic Gates Introduction - <topic>

Here is the outline I was thinking of: 3 hr lecture- 3 hr labs

1. Define what is meant by RTL 2 GDSII in general for ASIC applications.

A lecture to show the basics of a typical ASIC Design flow. You can explain this in the context of OpenROAD as well.

Also introduce the building blocks such as libraries, PDKS, rules, constraints etc briefly.


I have attached a set of slides based on our current presentation--this may be too complex but it gives you an idea of the flow. The design images can be substituted by a simpler example like GCD. (Github-> https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/tree/master/flow/designs/sky130hd/gcd)


2. Show the RTL- GDS flow in OpenROAD-flow-scripts

Explain briefly input/outputs at each stage and handoffs of the flow and the associated functional role.

e.g a Systems architect - designs the system given the components with a targeted design goal for power, performance, area

RTL engineer- Defines the register transfer level based on the architecture and synthesizes a netlist (Verilog, VHDL etc.) . We support Verilog.

3. Introduction to physical design - basic concepts of standard cell placement , creation of a power grid, i/o pins to connect to the external world,

goals - reducing wirelength


4. Some basic analysis like timing, area utilization, density etc. using the OpenROAD GUI.


5. Final chip handoff- importance of ensuring that this design can be made manufacturable based on skywater 130nm or GF180 pdk.


Lab demo - GCD (greatest common divisor) from ORFS Github-> https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/tree/master/flow/designs/sky130hd/gcd

I can help set you up with ORFS and share a simple demo  example.


Student project- Pick any design from the ORFS design repo, choose a design goal and improve that (area, utiization, timing etc)

Extra credit- Student selects any open source design core and completes the flow in ORFS.

- Submit a GitHub issue (problem found) or a fix  via a PR from the ORFS set of issues to contribute. This may be a huge stretch goal but students inclined towards software, scripts, document improvements can contribute.


Here's a MEMS foundry that was recently launched recently--something that could be very useful for your class.

https://science.xyz/news/launching-science-foundry


Here's the latest infor on Tiny Tapeout: https://www.youtube.com/watch?v=fblSVCPvCiY 


We should include a plan for student projects on Tiny Tapeout.



NSF Link to teacher Education research grant opportunities

Logic Gates Introduction - <topic>

This Lesson is coming soon - click here to be notified when it's available - Professional Development Newsletter

Logic Gates & Tiny Tapeout - Sites You Should Register, Get An Account or Sign-up for:

Reference, Attribution & Resources:

License - "Be A Hero"... Distribute Your Content As Open Source... That Is What I'm Doing...

The content on this site may have been pulled from other open source sites, but typically the interpretation and presentation is primarily the Intellectual Property of Jim Burnham, - TopClown@STEAMClown.org at www.steamclown.org and the Student curriculum can be found under the specific Mechatronics Engineering Units section of this web site.
If you do use my material, and make changes, I would appreciate getting a copy... because if you are making changes, it means that you think there is a better way to teach this… and I would really appreciate understanding that. Please send me feedback on my Questions or Feedback form. Please don’t hesitate to ask questions or comment.
You also should keep and include my STEAM Clown Logo and Copyright in any derivative works you create. I would appreciate if you would include one of these images found on my Steam Clown License page and link it to www.steamclown.org

Teachers - Unit, Module and Lesson Plans

If you are a teacher and want to connect and teach this Lesson or Module, discuss how I teach it, give me feedback, please contact me at TopClown@STEAMClown.org 

To access this Lesson Plan and the Teacher collaboration area, you will have needed to connect with me so I can Share the content with you.  Please go to  the Teachers & Partner Page, check out my Licensing and fill out my Collaboration and Curriculum Request Form.  I'll review and then grant you access to the requested areas and lesson plans if they exist.

If you have questions or feedback on how I can make a presentation, lesson, lab better please give use my Feedback Form.

Standards Alignments & Objectives:

I’ll work on getting these in, but it’s the last thing I want to work on :-) When I have them updated, I’ll move to the top of the Lesson Plan. 

Resource Attribution:
Sites Referenced or Summarized:

Images:


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