16:1 MUX
module mux2to1(
input I0, I1,
input S,
output Y
);
assign Y = (S == 1'b0) ? I0 : I1;
endmodule
module mux16to1(
input S3, S2, S1, S0,
input I15, I14, I13, I12,
input I11, I10, I9, I8,
input I7, I6, I5, I4,
input I3, I2, I1, I0,
output Y
);
wire Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7;
wire Z0, Z1, Z2, Z3;
wire W0, W1;
/* Stage 1 (S0) */
mux2to1 M0 (I0, I1, S0, Y0);
mux2to1 M1 (I2, I3, S0, Y1);
mux2to1 M2 (I4, I5, S0, Y2);
mux2to1 M3 (I6, I7, S0, Y3);
mux2to1 M4 (I8, I9, S0, Y4);
mux2to1 M5 (I10, I11, S0, Y5);
mux2to1 M6 (I12, I13, S0, Y6);
mux2to1 M7 (I14, I15, S0, Y7);
/* Stage 2 (S1) */
mux2to1 M8 (Y0, Y1, S1, Z0);
mux2to1 M9 (Y2, Y3, S1, Z1);
mux2to1 M10 (Y4, Y5, S1, Z2);
mux2to1 M11 (Y6, Y7, S1, Z3);
/* Stage 3 (S2) */
mux2to1 M12 (Z0, Z1, S2, W0);
mux2to1 M13 (Z2, Z3, S2, W1);
/* Stage 4 (S3) */
mux2to1 M14 (W0, W1, S3, Y);
endmodule
TOP TO DOWN APPROACH:--
// 2 : 1 Multiplexer
module mux2_1(
input I0, I1,
input S,
output Y
);
assign Y = (~S & I0) | (S & I1);
endmodule
// 4 : 1 Multiplexer (using 2 : 1 MUX)
module mux4_1(
input I0, I1, I2, I3,
input S1, S0,
output Y
);
wire w1, w2;
mux2_1 M1 (I0, I1, S0, w1);
mux2_1 M2 (I2, I3, S0, w2);
mux2_1 M3 (w1, w2, S1, Y);
endmodule
// 16 : 1 Multiplexer (Top-Down Structural)
module mux16_1(
input I0, I1, I2, I3, I4, I5, I6, I7,
I8, I9, I10, I11, I12, I13, I14, I15,
input S3, S2, S1, S0,
output Y
);
wire w1, w2, w3, w4;
// Four 4 : 1 MUX blocks
mux4_1 A1 (I0, I1, I2, I3, S1, S0, w1);
mux4_1 A2 (I4, I5, I6, I7, S1, S0, w2);
mux4_1 A3 (I8, I9, I10, I11, S1, S0, w3);
mux4_1 A4 (I12, I13, I14, I15, S1, S0, w4);
// Final 4 : 1 MUX
mux4_1 A5 (w1, w2, w3, w4, S3, S2, Y);
endmodule