Behavioral Description

BEHAVIORAL DESCRIPTION 

Verilog code :

module b_g (input [2:0]b, output reg [2:0]g);

always @(b) begin

    case (b)

        3'b000: g = 3'b000;

        3'b001: g = 3'b001;

        3'b010: g = 3'b011;

        3'b011: g = 3'b010;

        3'b100: g = 3'b110;

        3'b101: g = 3'b111;

        3'b110: g = 3'b101;

        3'b111: g = 3'b100;

        default: g = 3'b000;

    endcase

end

endmodule

Test Bench:--

module tb_b_g;

    reg  [3:0] b;

    wire [3:0] g;

    b_g DUT (b, g);

    initial begin

        for (integer i = 0; i < 16; i = i + 1) begin

            b = i[3:0];   // must be 4 bits

            #1;

        end

        $finish;

    end

endmodule

Output