Sequence Detector using Moore

THEORY:--

A sequence detector is a finite state machine that identifies a specific bit pattern within a serial data stream. For detecting the sequence 011, the detector transitions through states representing partial matches of the pattern. It starts by detecting 0, then 01, and finally 011. Once the full pattern is recognized, the detector outputs a 1 to indicate successful detection. This circuit is commonly designed using Mealy or Moore FSM models. 

State diagram 

• Verilog Code:-

module seq_detector_moore (

    input clk, 

    input rst_n, 

    input x,

    output reg z,

    output reg [3:0] state, 

    output reg [3:0] next_state

);

parameter A = 4'h1;

parameter B = 4'h2;

parameter C = 4'h3;

parameter D = 4'h4;

always @(posedge clk or negedge rst_n) begin

    if (!rst_n)

        state <= A;

    else

        state <= next_state;

end

always @(*) begin

    case (state)

        A: begin

            if (x == 0)

                next_state = B;

            else

                next_state = A;

            z = 1'b0;

        end

        B: begin

            if (x == 1)

                next_state = C;

            else

                next_state = B;

            z = 1'b0;

        end

        C: begin

            if (x == 1)

                next_state = D;

            else

                next_state = B;

            z = 1'b0;

        end

        D: begin

            if (x == 1)

                next_state = A;

            else

                next_state = B;

            z = 1'b1;

        end

    endcase

end

endmodule