Structural Description

Structural Description 

Verilog code ->

module FA (sum, cout, a, b, cin);

input a, b, cin;

output sum, cout;

assign sum  = a ^ b ^ cin;

assign cout = (a & b) | (b & cin) | (a & cin)

endmodule

module RCA_4bit (S, Cout, A, B, Cin);

input  [3:0] A, B;

input  Cin;

output [3:0] S;

output Cout;

wire c1, c2, c3;

FA f0 (S[0], c1, A[0], B[0], Cin);

FA f1 (S[1], c2, A[1], B[1], c1);

FA f2 (S[2], c3, A[2], B[2], c2);

FA f3 (S[3], Cout, A[3], B[3], c3);

endmodule

Testbench ->

module TB_RCA_4bit();

reg  [3:0] A, B;

reg  Cin;

wire [3:0] S;

wire Cout;

RCA_4bit dut (S, Cout, A, B, Cin);

initial begin

     A = 4'd0;  B = 4'd0;  Cin = 1'b0;

#10  A = 4'd2;  B = 4'd3;  Cin = 1'b0;

#10  A = 4'd4;  B = 4'd7;  Cin = 1'b0;

#10  A = 4'd8;  B = 4'd6;  Cin = 1'b1;

#10  A = 4'd15; B = 4'd15; Cin = 1'b0;

#10  A = 4'd9;  B = 4'd5;  Cin = 1'b1;

#20  $finish;

end

endmodule

Output:-