VERILOG CODE :--

module tff(q,qb,t,clk);

input t,clk;

output q,qb;

reg q=0;

reg qb=1;

always @(posedge clk)

begin

    if (t==0)

        q=q;

    else

        q=~q;

    qb<=~q;

end

endmodule

TEST BENCH:--

module tb_tff();

wire q,qb;

reg t,clk;

tff dux(q,qb,t,clk);

initial

begin

clk = 0;

repeat(10)

begin

    #5 clk =~clk;

end

end

initial

begin

t = 0;

#10 t = 1;

#10 t = 0;

#10 t = 1;

#20 $finish;

end

endmodule

OUTPUT WAVEFORM:

RTL