• Verilog Code:-

module bin_decimal(gfedcba, b, en);

input [2:0] b;

output reg [6:0] gfedcba;

output reg [7:0] en;

always @(b)

begin

    en = 8'b11111110;

    case(b)

        3'b000: gfedcba = 7'b1000000;

        3'b001: gfedcba = 7'b1111001;

        3'b010: gfedcba = 7'b0100100;

        3'b011: gfedcba = 7'b0110000;

        3'b100: gfedcba = 7'b0011001;

        3'b101: gfedcba = 7'b0010010;

        3'b110: gfedcba = 7'b0000010;

        3'b111: gfedcba = 7'b1111000;

    endcase

end

endmodule