Synchronous Up

THEORY:--

All flip-flops in a synchronous up counter are triggered at the same time by a common clock.
It counts upward in binary, increasing by 1 on each clock pulse.
Flip-flops toggle based on the condition that all lower-order bits are 1.
Faster and more reliable than asynchronous counters due to no ripple delay.

CIRCUIT DIAGRAM AND WAVEFORMS:--

VERILOG CODE:--

module sync_uc(q, clk, reset);

input clk, reset;

output [3:0] q;

reg [3:0] q;

reg [27:0]clk_div;

wire clk1;

always@ (posedge clk)

clk_div=clk_div+1;

assign clk1=clk_div[24];

always @ (posedge clk1)

begin

if(reset==1)

q=4'b000;

else

q=q+1;

end

endmodule

TEST BENCH:--

module tb_sync_uc;

wire [3:0] q;

reg clk ,reset;

sync_uc x1(q,clk,reset);

initial

begin

clk=0;

repeat(20)

#5 clk=~clk;

end

initial

begin

reset=1;

#20 reset=0;

#500 reset=1;

end

endmodule

OUTPUT WAVEFORM:--

RTL

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