Verilog Code :

module Excess03_BCD(B,E);

input [3:0] E;

output [3:0] B;

assign B[0] = E[0]^E[1] ;

assign B[1] = E[1]^E[2] ;

assign B[2] = E[2]^E[3];

assign B[3] = E[3];

endmodule

Test bench :

module TB_Excess03_BCD();

reg [3:0] E;

wire [3:0] B;

Excess03_BCD dux(B,E);

initial 

begin

      E=4'd0;

     #10 E=4'd1;

     #10 E=4'd2;

     #10 E=4'd3;

     #10 E=4'd4;

     #10 E=4'd5;

     #10 E=4'd6;

     #10 E=4'd7;

     #10 E=4'd8;

     #10 E=4'd9;

     #10 E=4'd10;

     #10 E=4'd11;

     #10 E=4'd12;

     #10 E=4'd13;

     #10 E=4'd14;

     #10 E=4'd15;

     #20 $finish();

     end

endmodule

Output