Dataflow Description

Verilog Code 

module array_multiplier(

input [1:0] A,

input[1:0] B,

output[3:0] P);

wire a0b0,a0b1,a1b0,a1b1;

wire sum1,sum2,carry1,carry2;

//Partial product

assign a0b0=A[0]&B[0];

assign a0b1=A[0]&B[1];

assign a1b0=A[1]&B[0];

assign a1b1=A[1]&B[1];

//First level of addition

assign sum1=a0b1^a1b0;

assign carry1=a0b1&a1b0;

//Second level

assign sum2=a1b1^carry1;

assign carry2=a1b1&carry1;

//Final product

assign P[0]=a0b0;

assign P[1]=sum1;

assign P[2]=sum2;

assign P[3]=carry2;

endmodule

Test bench code:

module tb_array_multiplier();

reg[1:0] A;

reg[1:0] B;

wire[3:0] P;

array_multiplier DUT(A,B,P);

initial 

begin

    A=2'b00;  B=2'b00;

#10 A=2'b01;  B=2'b01;

#10 A=2'b10;  B=2'b01;

#10 A=2'b11;  B=2'b11;

#20 $finish();

end

endmodule

OUTPUT: