Dataflow Description

Verilog Code

module cla_1(

    input  wire [3:0] a, b,   // 4-bit operands

    input  wire cin,           // carry-in

    output wire [3:0] sum,     // 4-bit sum

    output wire cout);           

    wire [3:0]p, g;   // propagate and generate

    wire c1, c2, c3;   // internal carries

    // Propagate and generate

    assign p = a ^ b;

    assign g = a & b;

    // Carry logic

    assign c1 = g[0] | (p[0] & cin);

    assign c2 = g[1] | (p[1] & g[0]) | (p[1] & p[0] & cin);

    assign c3 = g[2] | (p[2] & g[1]) | (p[2] & p[1] & g[0]) | (p[2] & p[1] & p[0] & cin);

    assign cout = g[3] | (p[3] & g[2]) | (p[3] & p[2] & g[1]) | (p[3] & p[2] & p[1] & g[0]) | (p[3] & p[2] & p[1] & p[0] & cin);

    // Sum

    assign sum[0] = p[0] ^ cin;

    assign sum[1] = p[1] ^ c1;

    assign sum[2] = p[2] ^ c2;

    assign sum[3] = p[3] ^ c3;

endmodule

Test bench code:

module tb_cla_1();

    reg [3:0] a, b;

    reg cin;

    wire [3:0] sum;

    wire cout;

    // Instantiate CLA

    cla_1 DUT(a,b,cin,sum,cout);

    initial begin

        // Test cases

        a = 4'b0000; b = 4'b0000; cin = 0; #10;

        a = 4'b0001; b = 4'b0010; cin = 0; #10;

        a = 4'b0101; b = 4'b0011; cin = 0; #10;

        a = 4'b1111; b = 4'b0001; cin = 0; #10;

        a = 4'b1010; b = 4'b0101; cin = 1; #10;

        a = 4'b1111; b = 4'b1111; cin = 1; #10

       #20 $finish;

    end

endmodule

OUTPUT: