Dataflow Description

module MUX_81(

    output y,

    input s2, s1, s0,

    input d7, d6, d5, d4, d3, d2, d1, d0

);

    assign y = (~s2 & ~s1 & ~s0 & d0) |

               (~s2 & ~s1 &  s0 & d1) |

               (~s2 &  s1 & ~s0 & d2) |

               (~s2 &  s1 &  s0 & d3) |

               ( s2 & ~s1 & ~s0 & d4) |

               ( s2 & ~s1 &  s0 & d5) |

               ( s2 &  s1 & ~s0 & d6) |

               ( s2 &  s1 &  s0 & d7);

endmodule

Test Bench:

module tb_MUX_81();

    reg s2, s1, s0;

    reg d7, d6, d5, d4, d3, d2, d1, d0;

    wire y;

    MUX_81 uut (y, s2, s1, s0,d7, d6, d5, d4,d3, d2, d1, d0);

    initial begin

        s2 = 0; s1 = 0; s0 = 0;

        d0=0; d1=0; d2=0; d3=0; d4=0; d5=0; d6=0; d7=0;

        #10 d0 = 1; s2=0; s1=0; s0=0;

        #10 d1 = 1; s2=0; s1=0; s0=1;

        #10 d2 = 1; s2=0; s1=1; s0=0;

        #10 d3 = 1; s2=0; s1=1; s0=1;

        #10 d4 = 1; s2=1; s1=0; s0=0;

        #10 d5 = 1; s2=1; s1=0; s0=1;

        #10 d6 = 1; s2=1; s1=1; s0=0;

        #10 d7 = 1; s2=1; s1=1; s0=1;

        #20 $finish;

    end

endmodule

• Output:-