Behavioral Description

BEHAVIORAL DESCRIPTION 

Verilog code:--

module BCD_Excess03(B,E);

input [3:0] B;

output [3:0] E;

assign E[0] = B[0]^B[1] ;

assign E[1] = B[1]^B[2] ;

assign E[2] = B[2]^B[3];

assign E[3] = B[3];

endmodule

Test bench:--

module TB_BCD_Excess03();

reg [3:0] B;

wire [3:0] E;

BCD_Excess03 dux(B,E);

initial 

begin

      B=4'd0;

     #10 B=4'd1;

     #10 B=4'd2;

     #10 B=4'd3;

     #10 B=4'd4;

     #10 B=4'd5;

     #10 B=4'd6;

     #10 B=4'd7;

     #10 B=4'd8;

     #10 B=4'd9;

     #10 B=4'd10;

     #10 B=4'd11;

     #10 B=4'd12;

     #10 B=4'd13;

     #10 B=4'd14;

     #10 B=4'd15;

     #20 $finish();

     end

endmodule

OUTPUT WAVEFORM: