Behavioral Description

BEHAVIORAL DESCRIPTION 

module mux4_1 (

    input  [3:0] I,   // 4 inputs

    input  [1:0] S,   // 2-bit select

    output reg Y

);

    always @(I or S)

    begin

        case (S)

            2'b00: Y = I[0];

            2'b01: Y = I[1];

            2'b10: Y = I[2];

            2'b11: Y = I[3];

            default: Y = 1'bx;

        endcase

    end

endmodule

Test Bench:--

module tb_mux4_1;

  reg  [3:0] I;

  reg  [1:0] S;

  wire       Y;

  // Instantiate 4:1 MUX

  mux4_1 uut (.I(I), .S(S), .Y(Y));

  initial

  begin

    I = 4'b1010;  // test input pattern

    S = 2'b00; #10;

    S = 2'b01; #10;

    S = 2'b10; #10;

    S = 2'b11; #10;

    $finish;

  end

endmodule

OUTPUT