Dataflow Description

Verilog Code 

module mux4_1(

    input wire [3:0] d,

    input wire [1:0] s,

    output wire y

);

assign y = d[s];

endmodule

Test Bench:

module tb_mux4_1();

reg [3:0] d;

reg [1:0] s;

wire y;

mux4_1 DUT (d,s,y);

initial 

begin

    d = 4'b1010;

    s = 2'b00; #10;

    s = 2'b01; #10;

    s = 2'b10; #10;

    s = 2'b11; #10;

    #10 $finish;

end

endmodule

• Output:-