Embedded Files
ASynchronous Down
ASynchronous Down
THEORY:--
An asynchronous down counter is a sequential circuit where only the first flip-flop is clocked externally, and each subsequent flip-flop is triggered by the previous stage’s output.
It counts downward in binary, decreasing the count by 1 on each clock pulse.
The counting action “ripples” through the flip-flops, causing cumulative propagation delay.
It is easy to design but slower and less reliable than synchronous down counters due to ripple effects.
CIRCUIT DIAGRAM:--
WAVEFORM:--
VERILOG CODE:--
module counter4(q,clk,reset);
input clk,reset;
output [3:0]q;
reg [3:0]q;
always@(posedge clk or posedge reset);
begin
if(reset==1)
q=4'b0000;
else
q=q-1;
end
endmodule
TEST BENCH:--
module tb_counter4;
wire [2:0]q;
reg clk,reset;
counter4 x1(q,clk,reset);
initial begin
clk=0;
repeat(20)
#5 clk=~clk;
end
initial begin
reset=1;
#20 reset=0;
#500 reset=1;
end
endmodule
OUTPUT WAVEFORM:--
RTL
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