Theory:--

• A random counter generates a sequence of numbers that does not follow a fixed counting order like up or down counting.
  
  

• The next count value depends on a predefined logic, feedback, or pseudo-random algorithm.
  
  

• Such counters are commonly implemented using LFSRs (Linear Feedback Shift Registers) in digital systems.
  
  

• Random counters are used in encryption, testing, simulations, and digital security applications.

🔁 Sequence: 5 → 4 → 7 → 6 → 2 → 1 → 3 → repeat 

Circuit Diagram:-- 

Verilog Code:--

module seq_counter(q, clk, reset);

input clk, reset;

output [2:0] q;

reg [2:0] q;

always @(posedge clk or posedge reset)

begin

    if (reset == 1)

        q = 3'd5;          // start from 5

    else begin

        case (q)

            3'd5: q = 3'd4;

            3'd4: q = 3'd7;

            3'd7: q = 3'd6;

            3'd6: q = 3'd2;

            3'd2: q = 3'd1;

            3'd1: q = 3'd3;

            3'd3: q = 3'd5;

            default: q = 3'd5;

        endcase

    end

end

endmodule

Test Bench:--

module tb_seq_counter;

wire [2:0] q;

reg clk, reset;

seq_counter x1(q, clk, reset);

initial begin

    clk = 0;

    repeat (20)

        #5 clk = ~clk;

end

initial begin

    reset = 1;

    #20 reset = 0;

    #500 reset = 1;

end

endmodule

OUTPUT WAVEFORM:--

RTL