Verilog Code :

module Gray_Bin(B,G);

input [3:0] G;

output [3:0] B;

assign B[0] = G[0]^G[1] ;

assign B[1] = G[1]^G[2] ;

assign B[2] = G[2]^G[3];

assign B[3] = G[3];

endmodule

Test bench :

module TB_Gray_Bin();

reg [3:0] G;

wire [3:0] B;

Gray_Bin dux(B,G);

initial 

begin

      G=4'd0;

     #10 G=4'd1;

     #10 G=4'd2;

     #10 G=4'd3;

     #10 G=4'd4;

     #10 G=4'd5;

     #10 G=4'd6;

     #10 G=4'd7;

     #10 G=4'd8;

     #10 G=4'd9;

     #10 G=4'd10;

     #10 G=4'd11;

     #10 G=4'd12;

     #10 G=4'd13;

     #10 G=4'd14;

     #10 G=4'd15;

     #20 $finish();

     end

endmodule

Output