Sequence Detector using Mealy

Theory:--

A Mealy 011 sequence detector monitors a serial input and outputs 1 immediately when the pattern 011 is received.
It uses three states to track the partial matches: 0, 01, and final 011.
The output becomes 1 when the machine is in state 01 and the current input is 1.
It supports overlapping patterns so consecutive 011 sequences can be detected.

State diagram 

• Verilog Code:-

module seq_detector_mealy_010 (

    input clk,

    input rst_n,

    input x,

    output reg z,

    output reg [3:0] state,

    output reg [3:0] next_state

);

parameter A = 4'h1;

parameter B = 4'h2;

parameter C = 4'h3;

reg z_next;

always @(negedge clk or negedge rst_n) begin

    if (!rst_n) begin

        state <= A;

        z <= 1'b0;

    end

    else begin

        state <= next_state;

        z <= z_next;

    end

end

always @(posedge clk) begin

    next_state = state;

    z_next = 1'b0;

    case (state)

        A: begin

            if (x == 0)

                next_state = B;

        end

        B: begin

            if (x == 1)

                next_state = C;

            else

                next_state = B;

        end

        C: begin

            if (x == 0) begin

                next_state = B;

                z_next = 1'b1;

            end

            else

                next_state = A;

        end

    endcase

end

endmodule