THEORY:--

• A synchronous down counter is a sequential circuit where all flip-flops receive the clock signal simultaneously.
  
  

• It counts downward in binary, decreasing the count by 1 on each clock pulse.
  
  

• Each flip-flop toggles when all lower-order bits are 0 (instead of 1 as in up counters).
  
  

• It offers high-speed operation with no ripple delay, making it more reliable than asynchronous down counters.

CIRCUIT DIAGRAM:--

WAVEFORMS:--  

VERILOG CODE:--
module counter4(q,clk,reset);

input clk,reset;

output [3:0]q;

reg [3:0]q;

always@(posedge clk);

begin 

if(reset==1)

q=4'b0000;

else

q=q-1;

end 

endmodule

TEST BENCH:--

module tb_counter4;

wire [3:0]q;

reg clk,reset;

counter4 x1(q,clk,reset);

initial begin

clk=0;

repeat(20)

#5 clk=~clk;

end

initial begin 

reset=1;

#20 reset=0;

#500 reset=1;

end 

endmodule

OUTPUT WAVEFORM:--

RTL