Behavioral Description

module mux8_1 (

    input  [7:0] I,   // 8 inputs

    input  [2:0] S,   // 3-bit select

    output reg Y

);

    always @(I or S)

    begin

        case (S)

            3'b000: Y = I[0];

            3'b001: Y = I[1];

            3'b010: Y = I[2];

            3'b011: Y = I[3];

            3'b100: Y = I[4];

            3'b101: Y = I[5];

            3'b110: Y = I[6];

            3'b111: Y = I[7];

            default: Y = 1'bx;

        endcase

    end

endmodule

Test Bench:--

module tb_mux8_1;

  reg  [7:0] I;

  reg  [2:0] S;

  wire       Y;

  // Instantiate 8:1 MUX

  mux8_1 uut (.I(I), .S(S), .Y(Y));

  initial

  begin

    I = 8'b11001010;  // test input pattern

    S = 3'b000; #10;

    S = 3'b001; #10;

    S = 3'b010; #10;

    S = 3'b011; #10;

    S = 3'b100; #10;

    S = 3'b101; #10;

    S = 3'b110; #10;

    S = 3'b111; #10;

    $finish;

  end

endmodule

OUTPUT