Behavioral Description

BEHAVIORAL DESCRIPTION 

module ex3_bcd(clk, ex3, bcd);

input clk;

input [3:0] ex3;

output reg [3:0] bcd;

reg [27:0] clk_div = 0;

wire clk1;

always @(posedge clk)

    clk_div = clk_div + 1;

assign clk1 = clk_div[24];

always @(posedge clk1)

begin

    case (ex3)

        4'b0011: bcd = 4'b0000;   // 3  → 0

        4'b0100: bcd = 4'b0001;   // 4  → 1

        4'b0101: bcd = 4'b0010;   // 5  → 2

        4'b0110: bcd = 4'b0011;   // 6  → 3

        4'b0111: bcd = 4'b0100;   // 7  → 4

        4'b1000: bcd = 4'b0101;   // 8  → 5

        4'b1001: bcd = 4'b0110;   // 9  → 6

        4'b1010: bcd = 4'b0111;   // 10 → 7

        4'b1011: bcd = 4'b1000;   // 11 → 8

        4'b1100: bcd = 4'b1001;   // 12 → 9

        default: bcd = 4'b0000;

    endcase

end

endmodule

Test Bench:--

module tb_excess3_bcd;

reg [3:0]e;

wire [3:0]bcd;

excess3_bcd dut(e,bcd);

integer i;

initial

begin

for(i=3;i<13;i=i+1)

begin

e=i[3:0];

#10;

end 

$finish;

end

endmodule

OUTPUT WAVEFORM:--