Behavioral Description

BEHAVIORAL DESCRIPTION 

Verilog code:--

module xor_chain_df (

input G3, G2, G1, G0,  // Inputs

output B3, B2, B1, B0   // Outputs

  );

assign B3 = G3;

assign B2 = B3 ^ G2;

assign B1 = B2 ^ G1;

assign B0 = B1 ^ G0;

endmodule

Test bench:--

module tb_xor_chain_df;

reg G3, G2, G1, G0;

wire B3, B2, B1, B0;

xor_chain_df uut (G3, G2, G1, G0, B3, B2, B1, B0);

initial 

begin

GO=0;G1=0;G2=0;G3=0;

….

…

GO=1;G1=1;G2=1;G3=1

$finish;

end

endmodule