Embedded Files
ASynchronous Up
ASynchronous Up
THEORY:--
An asynchronous up counter is a sequential circuit where only the first flip-flop receives the external clock, and each subsequent flip-flop is triggered by the output of the previous one.
It counts upward in binary, increasing the count by 1 with each input clock pulse.
Because flip-flops do not switch simultaneously, propagation delay accumulates as the count ripples through the stages.
It is simple and low-cost but slower and less accurate than synchronous counters due to ripple delay.
CIRCUIT DIAGRAM AND WAVEFORMS:
VERILOG CODE:--
module counter4(q,clk,reset);
input clk,reset;
output [3:0]q;
reg [3:0]q;
always@(posedge clk or posedge reset);
begin
if(reset==1)
q=4'b0000;
else
q=q+1;
end
endmodule
TEST BENCH:--
module tb_counter4;
wire [2:0]q;
reg clk,reset;
counter4 x1(q,clk,reset);
initial begin
clk=0;
repeat(20)
#5 clk=~clk;
end
initial begin
reset=1;
#20 reset=0;
#500 reset=1;
end
endmodule
OUTPUT WAVEFORM:--
RTL
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