Open Ended Project

INTRODUCTION

Processors form the core of all modern digital and embedded systems, as they are responsible for executing instructions and performing computations. Among different processor architectures, RISC (Reduced Instruction Set Computer) architecture is widely used due to its simplicity, high performance, and efficient hardware utilization. RISC processors are designed with a small set of simple instructions, which allows faster execution and easier implementation compared to complex instruction set architectures.

In this project, a 4-bit RISC processor is designed and simulated using Verilog Hardware Description Language. The processor is capable of executing basic arithmetic and logical operations such as addition, subtraction, AND, OR, XOR, NOT, and shift operations. The instruction to be executed is selected using a 3-bit opcode, and the processor operates on 4-bit input data values.

The internal operation of the processor follows a five-stage instruction execution cycle, namely Instruction Fetch, Instruction Decode, Execute, Memory Access, and Write Back. Each stage is executed in one clock cycle and is controlled using a finite state machine. This stage-wise execution helps in understanding how instructions flow through a processor and how results are generated over multiple clock cycles.

The design is verified using a Verilog testbench, and simulation waveforms are analysed to observe correct stage transitions and output behaviour. This project provides a clear and practical understanding of basic processor architecture, control logic, and Verilog-based digital system design.

VERILOG CODE

module risc_4bit (

    input clk,

    input reset,

    input [3:0] data_a,

    input [3:0] data_b,

    input [2:0] opcode,  

    output reg [3:0] alu_result,

    output reg [4:0] stage_led

);

    // STATE ENCODING

    parameter IF_STAGE  = 3'd0;

    parameter ID_STAGE  = 3'd1;

    parameter EX_STAGE  = 3'd2;

    parameter MEM_STAGE = 3'd3;

    parameter WB_STAGE  = 3'd4;

    reg [2:0] state;

    reg [3:0] reg_a;

    reg [3:0] reg_b;

    reg [3:0] alu_out;

    // FSM IMPLEMENTATION

    always @(posedge clk or posedge reset) begin

     if (reset) begin

         state  <= IF_STAGE;

         stage_led  <= 5'b00000;

         alu_result <= 4'd0;

         reg_a  <= 4'd0;

         reg_b  <= 4'd0;

         alu_out <= 4'd0;

     end else begin

         case (state)

             // -------- IF --------

             IF_STAGE: begin

                 stage_led <= 5'b00001;

                 state <= ID_STAGE;

             end

             // -------- ID --------

             ID_STAGE: begin

                 stage_led <= 5'b00010;

                 reg_a <= data_a;

                 reg_b <= data_b;

                 state <= EX_STAGE;

             end

             // -------- EX --------

             EX_STAGE: begin

                 stage_led <= 5'b00100;

                 case (opcode)

                     3'b000: alu_out <= reg_a + reg_b; // ADD

                     3'b001: alu_out <= reg_a - reg_b; // SUB

                     3'b010: alu_out <= reg_a & reg_b; // AND

                     3'b011: alu_out <= reg_a | reg_b; // OR

                     3'b100: alu_out <= reg_a ^ reg_b; // XOR

                     3'b101: alu_out <= ~reg_a;    // NOT

                     3'b110: alu_out <= reg_a << 1; // SHL

                     3'b111: alu_out <= reg_a >> 1; // SHR

                     default: alu_out <= 4'd0;

                 endcase

                 state <= MEM_STAGE;

             end

             // -------- MEM --------

             MEM_STAGE: begin

                 stage_led <= 5'b01000;

                 state <= WB_STAGE;

             end

             // -------- WB --------

             WB_STAGE: begin

                 stage_led  <= 5'b10000;

                 alu_result <= alu_out;

                 state <= IF_STAGE;

             end

             default: state <= IF_STAGE;

         endcase

     end

    end

endmodule

VERILOG TESTBENCH

module tb_risc_4bit;

 reg clk;

 reg reset;

reg [3:0] data_a;

 reg [3:0] data_b;

 reg [2:0] opcode;

wire [3:0] alu_result;

wire [4:0] stage_led;

// DUT INSTANTIATION

risc_4bit DUT (

     .clk(clk),

     .reset(reset),

     .data_a(data_a),

     .data_b(data_b),

     .opcode(opcode),

     .alu_result(alu_result),

     .stage_led(stage_led)

);

// CLOCK GENERATION

initial clk = 0;

always #5 clk = ~clk;   // 10ns clock period

// TEST SEQUENCE

initial begin

     reset  = 1;

     data_a = 4'd0;

     data_b = 4'd0;

     opcode = 3'd0;

     #20;

     reset = 0;

     // ---------- ADD ----------

     data_a = 4'd5;

     data_b = 4'd3;

     opcode = 3'b000;   // ADD

     #50;

     // ---------- SUB ----------

     data_a = 4'd9;

     data_b = 4'd4;

     opcode = 3'b001;   // SUB

     #50;

     // ---------- AND ----------

     data_a = 4'b1010;

     data_b = 4'b1100;

     opcode = 3'b010;   // AND

     #50;

     // ---------- OR ----------

     opcode = 3'b011;   // OR

     #50;

     // ---------- XOR ----------

     opcode = 3'b100;   // XOR

     #50;

     // ---------- NOT ----------

     opcode = 3'b101;   // NOT A

     #50;

     // ---------- SHIFT LEFT ----------

     opcode = 3'b110;   // SHL

     #50;

     // ---------- SHIFT RIGHT ----------

     opcode = 3'b111;   // SHR

     #50;

     $stop;

end

// MONITOR

initial begin

     $monitor(

         "Time=%0t | StageLED=%b | Opcode=%b | A=%d | B=%d | ALU_Result=%d",

         $time, stage_led, opcode, data_a, data_b, alu_result

     );

end

endmodule

SYNTHESIS REPORT

TIMING REPORT

OUTPUT

REPORT