Verilog Code
module t_ff (
output Q,
input clk,
input rst,
input T
);
wire D, nQ;
not (nQ, Q);
xor (D, Q, T);
d_ff dff1 (Q, clk, rst, D);
endmodule
module d_ff (
output reg Q,
input clk,
input rst,
input D
);
always @(posedge clk or posedge rst)
begin
if (rst)
Q <= 1'b0;
else
Q <= D;
end
endmodule
module sync_up_counter #
(
parameter N = 4
)
(
input clk,
input rst,
output [N-1:0] Q
);
wire [N-1:0] T;
assign T[0] = 1'b1;
genvar i;
generate
for (i = 1; i < N; i = i + 1)
begin : T_GEN
and (T[i], Q[i-1], T[i-1]);
end
endgenerate
generate
for (i = 0; i < N; i = i + 1)
begin : FF_GEN
t_ff TFF (Q[i], clk, rst, T[i]);
end
endgenerate
endmodule