Dataflow Description

module mux_16_1(

    input wire [15:0] d,   

    input wire [3:0] s,  

    output  y          

);

    assign y = d[s];

endmodule

Test Bench:

module tb_mux_16_1();

    reg [15:0] d;

    reg [3:0] s;

    wire y;

    mux_16_1 DUT(d,s,y);

    initial 

    begin

        d = 16'b1010101010101010;  

        s = 4'b0000; #10;

        s = 4'b0001; #10;

        s = 4'b0010; #10;

        s = 4'b0011; #10;

        s = 4'b0100; #10;

        s = 4'b0101; #10;

        s = 4'b0110; #10;

        s = 4'b0111; #10;

        s = 4'b1000; #10;

        s = 4'b1001; #10;

        s = 4'b1010; #10;

        s = 4'b1011; #10;

        s = 4'b1100; #10;

        s = 4'b1101; #10;

        s = 4'b1110; #10;

        s = 4'b1111; #10;

        #10 $finish;

    end

endmodule

• Output:-