VERILOG CODE:-- 

module srff(q,qb,s,r,clk);

input s,r,clk;

output q,qb;

reg q=0;

reg qb=1;

always @(posedge clk)

begin

    if (s==0 && r==0)

        q=q;

    else if (s==1 && r==0)

        q=1;

    else if (s==0 && r==1)

        q=0;

    else

        q=q;   // invalid condition (S=1,R=1) normally avoided

    qb <= ~q;

end

endmodule

TESTBENCH :--

module tb_srff();

wire q,qb;

reg s,r,clk;

srff dux(q,qb,s,r,clk);

initial

begin

clk = 0;

repeat(10)

begin

    #5 clk =~clk;

end

end

initial

begin

s = 0; r = 0;

#10 s = 1; r = 0;

#10 s = 0; r = 1;

#10 s = 1; r = 1;

#20 $finish;

end

endmodule

OUTPUT WAVEFORM:--

RTL