Power Subsystem Design

Subsystem Design block diagram

The power design block diagrams are detailed below; The Electric power supply (EPS), consists

• the Direct energy transfer (DET) switches,

• Flight inhibit switches

• Battery protection circuit module (PCM)

• Power distribution system

• Deployment timer

Whilst and the EPS controller, consists a low power microcontroller with essential peripherals for monitoring and managing the functions of the power subsystem. In this scheme, the EPS is used to connect solar strings, batteries and spacecraft power loads to one bus where energy flows as needed.

The solar array is made up of 21 photovoltaic (PV) cells, arranged in 7 parallel strings of 3 cells each (3S7P configuration). Each solar string includes bypass diodes and is independently connected to the main power bus (MPB) through a switch to charge the battery pack. Therefore, battery charge regulation is achieved by sequential switching regulation, with no maximum power point trackers.

The battery pack is made up of 6 cells, arranged as a series connection between 2 sets of 3 parallel cells (3P2S configuration). It connects to the MPB, where it stores the energy generated by the solar strings. Battery cell chemistry is LiFePO4, and a Protection circuit module (PCM) monitors cells for over-voltage, under-voltage as well as pack over-current conditions to protect against abuse.

The power distribution system is made up of spacecraft loads that draw power directly from the unregulated MPB through 7 independent switches, 1 regulated line and 1 unregulated-unswitched line as shown in the block diagram. The switched lines have software current limits enforced by the EPS controller, as well as latching current limits enforced by hardware.

The flight inhibit switches are used to hold the satellite in a deactivated state when required, these consist two series solid state relays (SSRs) placed on the MPB prior to the power distribution system and a third SSR placed on the battery ground leg terminal. The flight inhibit switches are held off until released by combinational logic generated by the deployment timer, deployment switches and Remove before flight (RBF) pin.

The deployment timer is a mixed analog-digital circuit that controls the flight inhibit system. It consists of two analog timers programmed to assert an active high 30 minutes after power on, a digital IC that maintains a third 30 minute timer, votes on the output of all timers and combines this with reading the RBF state to determine whether to latch the Flight inhibit switches to an ON state.

Meanwhile, EPS telemetry is gathered by the EPS controller including:

• Solar string currents

• Battery voltage and current

• Critical load currents,

And finally, control signals are issued from the EPS controller to activate DET switches and spacecraft power loads.

Energy Generation - Photovoltaic cells

Photovoltaic (PV) cells are the primary source of power on the spacecraft. The PV cells are triple junction GaAs cells, with Ge substrate and Ag/Au contact metallization (Azur Space TJ Solar Cell Assembly 3G30A). The cells are pictured in Figure 3, with dimensions. Detailed information about the cells and array design can be found on the solar array design page.

Figure 4 shows the electrical connection of the solar strings. The specified cells include integrated bypass diodes, which allow current to flow safely in event of partial shading or string current mismatch. The electrical specifications detailed in the table are based on the 3S string configuration.

Energy Storage - Lithium iron phosphate (LFP) battery pack

Energy is stored onboard the spacecraft in a battery pack constructed from Lithium iron Phosphate cells. The specified cells are obtained from AA Portable Power corp. (IFR-18650EC-1.5Ah). Each cell has a rated nominal capacity of 1500 mAh and nominal potential difference of 3.2 V. The main reason for selecting LFP cells is to take advantage of its relative flat voltage profile, because the battery pack is the main source of capacitance on the unregulated MPB. Consequently, the operating voltage of the solar strings and spacecraft loads is equal to the battery pack voltage, the relatively flat voltage profile is therefore desirable.

Figure 5 shows the battery pack in a 2S3P configuration. Based on the given battery pack specifications, operating temperature control is crucial. As a result, two battery heaters are used from the Thermal subsystem to condition the batteries.

Energy consumption - Satellite subsystems

The Power module provides energy to operate itself and all spacecraft subsystems including: ADCS, CDH, COMS, PLD, Deployables (DPLY) and thermal heaters (HTR). The power module provides the raw battery voltage to all units, except the primary battery heaters which requires voltage regulation to 3.3 V. The power distribution system is controlled according to the spacecraft operations plan which defines the following modes:

• Post-ejection hold - Entered upon removal of RBF pin and subsequent actuation of deployment switches, only the 30 minute deployment timer receives power

• Detumble mode - In this mode, the EPS controller works with the ADCS controller to slow the tumble rate of the spacecraft

• Normal mode - This is the default mode of the power module (includes Science mode and Sun-pointing mode of the operations plan)

• Idle mode - This mode is used during commissioning activities (ADCS and payload are off)

• Low power mode - Entered when the battery SoC drops to 40 % or below

• Survival mode - Entered when the battery SoC drops to 30 % or below

• Critical hold mode - Entered when the battery SoC drops to 25 % or below

The power module is primarily designed to support normal mode operations, whose peak power requirements are summarized in table 2.

Latch-off hardware current limits are enforced by the load switch integrated circuit in the event of excess faults as secondary protection, while lower value software current limits are imposed by the EPS controller as primary protection.

Power module avionics - Overview

Power module avionics consists of an Electric power supply (EPS) and its associated EPS controller. The EPS houses the main power bus (MPB), which connects Energy generation (solar strings), storage (batteries) and distribution components (load switches) together, using electronics circuits as well as sensors are used to monitor EPS quantities.

The EPS controller houses the power module processor, which controls battery charge regulation through the DET switches, load switching between operating modes and samples analog sensors.

The position and key interfaces of the power module avionics are depicted below. The EPS provides power to subsystem control boards, whilst sending analog sensor data to and receiving digital control commands from the EPS controller. Electrical ground support equipment (EGSE) capable of interfacing the EPS includes the ground battery chatger.

The EPS controller also receives power from the MPB and exchanges information with COMS/CDH/PLD controllers over CANBUS, and the ADCS control board through an SPI interface. Solar array thermistors placed on the wings and body of the spacecraft are also monitored by the EPS controller.

Power module avionics -EPS board

The Electric Power Supply (EPS) board (UMS-0110-A) is an electronics assembly that provides connects Energy generation (solar strings), storage (batteries) and distribution components (subsystems) on one bus called the main power bus (MPB). Harvested energy is used to charge batteries through a direct energy transfer (DET) circuit, while spacecraft loads on the MPB form the load distribution system. Each subsystem may further regulate the voltages it needs, doing so locally, outside the EPS.

The main power bus (MPB), connected through inhibit switches to the spacecraft loads is one of two parallel buses formed at the battery positive terminal. The other is an auxiliary power bus (APB) that provides power to the deployment timer and inhibit switch activation circuit before activation of the MPB. Finally, the EPS protects the battery pack using a protection circuit module to monitor fault conditions at the cell level.

EPS Battery charge regulation - Sequential switching regulation with DET

Each of the 7 solar strings interfaces to the main power bus through a direct energy transfer (DET) switch. This allows a direct low impedance connection between the batteries and the solar strings, with no maximum power point tracker (MPPT). Due to the absence of MPPT, the operating voltage of solar strings is fixed by the battery pack capacitance. Meaning that the energy generation system will often be operated at a point that does not maximize the amount of available power. However, this factor was taken into consideration in configuring the solar strings and battery pack. First, the battery pack was fixed, taking subsystem voltage needs into account, then the solar strings were configured such that the open circuit voltage would be higher than the battery operating voltage and the maximum power voltage as close as possible to the nominal battery voltage. This ensures that under ideal conditions, the operating point is decently close to the maximum obtainable power (nominal battery voltage is 6.4 V, whereas under ideal conditions, solar string max power voltage is 7.08 V).

The battery charge regulator (BCR) follows a sequential switching regulation scheme shown in Figure 7, where the voltage of the battery pack is monitored and regulated using a PI error amplifier, such that it does not exceed the specified End of charge (EOC) voltage. The BCR program runs on the EPS controller using measurements of the MPB bus voltage to control DET switches. when the MPB voltage is lower than the EOC limit, the error amplifier saturates and turns on all DET switches. As the battery voltage starts to approach the EOC limit, the error amplifier then starts to regulate the voltage by sequential commutation of the DET switches, thus modulating the power delivered to the battery pack. Since saturation of the error amplifier is built into the design and the error amplifier is a digital algorithm, EPS controller software will include integral windup implementation to prevent mismanagement of the battery voltage.

The DET switch is implemented using common source MOSFET switches, shown in Figure 8. In order to improve power utilization, considering that the DET configuration is not maximizing the power available to the system, the design avoids the use of dedicated bypass diodes, using instead the blocking capability of the DET switch to protect the solar strings from reverse currents when the DET switch is gated OFF. An Ideal diode controller is added to control the gate of the MOSFETs such that reverse current through the channel is also prevented. Sequential switching by the BCR is therefore controlled by enabling or disabling the ideal diode controller, and Analog current monitoring is added through an integrated circuit current shunt monitor that includes a current sense amplifier.

EPS Power Distribution - Main power bus (MPB)

The main power bus (MPB) is the most important power bus in the system. It is used for power harvesting and distribution and must avoid critical failures. The main capacitance on the MPB is provided by the battery pack, which dictates the MPB voltage. As such the MPB is an unregulated voltage bus. The main protective feature of the MPB is latch-off current limiting of loads bus loads (with exception of Thermal heaters and the Auxiliary power bus (APB)). Other protective features of the MPB include:

• Strategically placed Transient voltage suppressors (TVS)

• Ceramic capacitor bank

• Inrush current control of all bus consumers (except APB)

Figure 9 shows the load switch implementation block diagram, the switches are enabled from EPS controller, which also monitors currents and enforces software current limits and perfoms shutdowns according to modes of operation. The gate control circuit is embedded within the load switch IC limits inrush currents to acceptable levels.

EPS Power Distribution - Auxiliary power bus (APB)

The Auxiliary Power Bus (APB) is created from the MPB as a dedicated power rail for the deployment timer and inhibit switch system. It is further divided into two buses, an unswitched bus (APB1) that powers the Non-volatile latches of the deployment timer circuit and a switched bus (APB2), activated by a PMOS whose gate is controlled by the actuation of deployment switches and the RBF pin. The block diagram of Figure 10 shows the design of the APB.

APB1 is always active, while APB2 is only active when all deployment switches are closed and the RBF pin is removed. In the event of mechanical switch failure during the mission, and to facilitate ground testing, an alternate way of keeping APB2 alive is provided by the APB2_EN terminal, controlled by the deployment timer latch logic.

EPS Electrical inhibits and Deployment timer

The electrical inhibit system includes three solid state relays (SSR) placed as follows:

• SSR1 and SSR2 are placed in series between the MPB and all its loads.

• SSR3 is placed at the battery ground terminal as a ground leg inhibit

The deployment timer is a mixed analog-digital solution, two analog timers are set such that after 30 minutes, their output is held high and read by a low power 14-pin processor. The processor, which also runs an internally programmed digital timer, performs voting on timer outputs to determine when to change the state of the SSRs.

The intended operating sequence of the inhibit system is as follows:

• RBF pin is removed -> Nothing happens

• Deployment switches are actuated -> This connects battery negative to the ground point through SSR3 and activates APB2

• Timer circuit receives power -> 30 minute countdown resumes

• 30 minute timer completes -> Indicated by a majority 2 of 3 timer outputs

• SSRs 1 and 2 are activated -> All Non volatile latches are set to the ON state

• APB2_EN is asserted -> Allowing the spacecraft to remain ON in event of mechanical switch failure

The digital circuit also reads the RBF pin state. If the satellite is still on the ground, and the RBF pin is reinserted, an OFF state is written to the Non-volatile latches to shut down the satellite. In this way, removing the RBF pin always resets the 30 minute timers and the satellite will not function if the RBF is inserted. Non-volatile latches are used to ensure uninterrupted power supply, in the event of a watchdog initiated reboot of the digital component, or other unforeseen power glitches. The latches are only cleared during the 30 minute countdown or if the RBF pin is inserted, otherwise they are always engaged.

The flight inhibit switch system configuration shown in Figure 12, uses optically isolated solid state relays (SSR). The main advantage of this is the electrical isolation between the potentially high current paths and the low power controlling circuitry of the deployment timer, which simplifies drive requirements.

RFD for the Electrical Inhibit System

During the requirement reviews for the Power subsystem, we found out that our inhibit design is not compatible with requirement 4.2.1.3 of the NR-NRCSD-S0003 Rev- document. Our MSB power inhibit is controlled by software running on the EPS board's microcontroller which is not compliant with this requirement. Our RFD was approved by NanoRacks on May 18, 2022 as per document below.

EPS Battery protection

Cell level battery protection is implemented using two AP9101 integrated circuits. For each cell, the circuit includes a protection circuit monitor (PCM), and two protection FET switches connected in common drain configuration. One MOSFET is capable of blocking charge while the other blocks discharge current, hence they are denoted as charge (CHG) FET and discharge (DSG) FET. The PCM is an integrated circuit which includes a high accuracy voltage detection circuits monitors the cells, and controls the protection FETs in response to fault conditions. It is capable of overcharge, over-discharge, and overcurrent protection as follows:

Protection features summary:

• Over-charge detection voltage 3.650 V per cell (7.3 V pack), persisting for 1 second

• Over-charge release voltage - 3.450 V per cell (7.0 V pack),

• Over-discharge detection voltage - 2.100 V per cell (4.0V pack), persisting for 128 milliseconds

• Over-discharge release voltage - 2.300 V per cell (5.0 V pack)

• Over-current detection - +/- 3.500 A, persisting for 8 milliseconds

• Short-circuit detection - +/- 6.000 A, persisting for 280 microseconds

The battery PCM is intended to function as primary protection against over-discharge and short-circuit conditions, however it is only relied upon for secondary protection against overcharging. This is because charge voltage regulation is to be carried out by the battery charge regulator as primary over-voltage protection, this is why the overcharge limit of the selected PCM can be higher than the manufacturer recommendations (3.650 V per cell). It is also expected that the EPS controller and latching current limiters would act to prevent over current and short conditions before the battery PCM has to act.

Power module avionics - EPS controller

The EPS controller (UMS-0110-B) is responsible for managing the EPS. It controls battery charge regulation, power distribution, collects telemetry data, receives instructions from other modules and transmits data. Since the power module is the first system to be powered on, the EPS controller also controls post ejection detumbling.

The EPS controller is built around the MSP430FR2476 microcontroller from Texas Instruments. It is a low power 16-bit microcontroller unit, and is supported by two Analog to Digital Converter modules, and an SPI to CAN converter. The main functions of the EPS controller are to control battery charge regulation, control load switches, monitor the health of the EPS and communicate with COMS, CDH and PLD. The ADCs provides 24 channels for monitoring: 15 EPS sensor signals and 6 Analog thermistor. Thermistor locations can be found in the Thermal subsystem documentation.

The EPS controller is one of the loads on the MPB from which it draws power. However the voltage is further regulated using switched mode power supplies and low dropout regulators to levels required by the MCU and other peripherals. The MCU does not natively support CAN bus, hence an SPI to CAN converter is included in the design, which enables CAN communication with COMS and CDH. The ADCS subsystem does not support CAN bus, so it is interfaced using the SPI protocol.

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