Embedded Files
Introduction
Introduction
This page describes the software written for the power control unit's microprocessor. The code for the processor is written in C.
Key Requirements
Key Requirements
R-POW-0170: Communicate with ADCS during detumbling via SPI
R-POW-0844: Initiate idle operations when commanded by ground
R-POW-0845: Initiate low power mode when SOC reaches 40%
R-POW-0846: Initiate survival power mode when SOC reaches 30%
R-POW-0847: Initiate critical power mode when SOC reaches 25%
R-POW-1330: Shall not operate for minimum of 30 minutes when hazard potential exists
R-POW-1370, R-POW-0181: Communicate with CDH and Comms over the CAN bus
R-POW-1710: Continuous estimation of the battery SOC at any time
R-POW-1750: Undergo checkout activities after release from the deployer
PCU Microprocessor
PCU Microprocessor
Figure 1: The functional block diagram of the processor from its datasheet
The MSP430FR247x is an ultra-low power MCU. It promotes extended battery life and features 16-bit timers, four eUSCIs , a hardware multiplier, an RTC module and a 12-bit ADC. The CPU is integrated 16 registers where four of them, R0 to R3, are for program counter (PC). stack pointer (SP), status register (SR) and constant generator (CG) respectively. The rest are for general purposes.
Operating Modes
Operating Modes
The processor has one active mode and 5 low power modes as shown in Figure 2. An interrupt event can bring the MCU from the first three low power modes, execute any requests and make the MCU go back to the low power mode. The last two low power modes minimize the power consumption by disabling the core supply.
Figure 2: Operating modes for the MCU
Entering and Exiting the Different Power Modes
Entering and Exiting the Different Power Modes
The CPUOFF, OSCOFF, SCG0, and SCG1 bits in the status register help configure the first three low power modes. The values of these bits for different modes is in Table 1.
Table 1: Operation modes
Based on the Table, the following script helps enter and exit a power mode using interrupts. Here, LPM0 is shown as an example.
; Enter LPM0
BIS #GIE+CPUOFF, SR
; Execute requests
; Exit LPM0 Interrupt Service Routine
BIC #CPUOFF, 0(SP)
RETI
Clock System
Clock System
This system generates and distributes all the clock sources on the MCU. It has two configurations: Basic and advanced. There are upto 6 clock sources: XT1CLK, VLOCLK, REFOCLK, DCOCLK and MODCLK. For more details, please refer to the User Guide.
Load Shedding Algorithm
Load Shedding Algorithm
As mentioned on the design page, the PCU monitors the SOC of the battery to identify if there a low power mode is to be turned on. The SOC corresponding to different modes are:
Low power mode: 40% SOC - 6.44 V
Survival mode: 30% SOC - 6.4 V
Critical mode: 25% SOC - 6.36 V
Cut-off voltage is 7.08 V
While switching to a lower power mode is autonomous through the PCU based on the load shedding algorithm, moving back to a higher power mode requires a command from ground. There are exceptions when moving from the critical to survival mode since CDH and comms are off during the critical mode and for an upgrade from post-ejection to detumbling mode.
The PCU performs cumulative load shedding i.e. it takes into account the SOC for more than 400 s (worst case communication window) to make a decision to change modes. This is because instantaneous voltage changes could be the result of sudden, temporary and high current draws during a communication window or payload imaging. Protection against transient current and voltage changes is incorporated in the power subsystem design.
Battery state of charge estimation
Battery state of charge estimation
The PCU has a coulomb counter MAXIM DS27 that estimates the battery's SOC at any given time. But, as a backup, an algorithm (Figure 3) loosely based on the enhanced coulomb counting method is used. At any time t, the battery voltage and the current are measured by the PCU. In the figure:
fSOC is the maximum achievable SOC of the battery.
DOD is the depth of discharge, DOD(t_0) is the DOD at the initial time while SOC(t_0) is the SOC at the initial time t_0
V and I are the battery voltage and current at any given time t
Figure 3: SOC estimation algorithm
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