C&DH

Introduction

The Command and Data Handling (CDH) subsystem is responsible for providing onboard computer hardware that runs the flight software command and control tasks. its functional block diagram is as shown in Figure 1 below.

UMS-0077: CDH Electrical hardware assembly (Engineering Model )

The CDH hardware consists of the processor that runs the flight software command and control tasks as well as its associated peripherals. All CDH component parts are mounted on the CDH control board, forming the UMS-0077 assembly. The current design is the engineering model (EM) which will undergo rigorous functional testing in Phase C and D and provide a reference for the future flight model.

Figure 3 shows the basic electrical interfaces of the CDH control board with respect to other subsystem boards. For more details on CDH subsystem interfaces, refer to the CDH ICD and Satellite Harness systems. Figure 4 shows the block diagram of the CDH hardware, build around the SmartFusion 2 system on a chip (Soc). SoC embeds the ARM processor, FPGA fabric, Control Area Network (CAN) and Serial Peripheral Interface (SPI) modules that are used in the design.

The Altium Designer project for UMS-0077 EM can be downloaded here.

Microsemi's SmartFusion2 SoC is the main processing unit, this SmartFusion 2 is an ultra-low power, radiation tolerant SoC, with proven flight heritage [1]. The processing unit contains both a microcontroller subsystem (MSS) containing ARM Cortex-M3 as the hard-core processor and FPGA fabric, both of which are immune to single-event upsets.

Flight software will run on ARM Cortex M3, which is a 32-Bit processor that can execute 1.25 DMIPS/MHz. Running at 166-MHz, it can execute 207 DMIPS, which is enough for doing the satellite operations with a high margin. MSS also has a 64 KB embedded SRAM (eSRAM) as the general work memory, which has a Single Error Correction and Double Error Detection (SECDED) feature. As well as a 256 KB embedded nonvolatile memory (eNVM) as the boot Memory. The FPGA fabric provides a highly flexible platform for loading custom IP cores for SPI and CAN. The TQGI144 package allows for thermal expansion of the chip.

Based on requirement R-CDH-0002, At least 2 MB is required for image processing, so the Avalanche AS3016101 memory is designated for this purpose. For safeguard and system register memory, we use Everspin's MR25H40MDF MRAM sized at 4Mb, which is intrinsically immune to Single Event Upset (SEU) and qualified under AEC-Q100 [2]. Based on requirement R-CDH-0005, the CDH is expected to provide a mimimum of 100 MB for permanent data storage. Winbond's W25N01GVZEIG 1G-bit SPI Flash Memory is used for long term storage. 3 or 5 bitwise voting is used as a memory protection scheme and is qualified under AEC-Q100 [2].

One SPI soft-core in the FPGA fabric will interface with 8 channel ADC, MRAM, SRAM, flash memory, and RTC.

Some of the CDH computing concepts are:

• Flight software is capable of disabling the Watchdog timer.

• The CDH will load images from the camera modules over CAN Bus to the SRAM.

• A soft decryption core will be placed in FPGA fabric.

• A custom image processing soft-core will be placed in FPGA fabric.

• One CAN Bus will be placed in FPGA fabric.

Based on the previously described model philosophy, three CDH models will be built. Firstly, an Engineering Breadboard Model is built, intended to test major electrical components and functionality. Secondly, an Engineering Model is built, which inherits the final form of the engineering breadboard model, and is intended to retest all components from the engineering breadboard model and give flight software a testbed for software development on a finished unit. Finally, a fight model will be built with the highest grade components and will undergo all required flight acceptance readiness tests.

The UMS-0077 Engineering model consists of 6 layers with the stack up and via configurations, shown in Figure 6. It is followed by layer configurations for each layer.

UMS-0267 Flight Model Design

The CDH FM design was derived from the CDH EM design. Upon testing the CDH EM model, some errors in the design were identified which required changes for the FM. The core of the design matches the UMS-0077 Engineering Model including the layout, communication protocols, and critical Integrated Circuits (Flash memory, MRAM, SRAM & SmartFusion SoC), however, some changes to hardware were necessary to fix errors identified while testing the CDH EM model.

These changes are outlined in the spreadsheet below. A summary of the changes includes:

1. Removing connectors and jumper pins not required on the FM.

2. Remove LEDs and physical reset switch.

3. Changing the footprint of U5 and U6 to match the correct dimensions from their datasheets.

4. Replacing the original spec'd out Avalanche SRAM (part #: AS3016101-0010X0PSAR) to that tested on the Engineering Model (Avalanche SRAM part #: AS3016204-0108X0PSAY)

5. Address two floating signals: VDDI3 and ADC_VREF.

6. Changing the pin assignments for Flash2 and ADC to allow FSW to use In-Application Programming.

UMS-0267 Electrical schematics (FM)

The design schematics for the CDH FM model are embedded in the PDF below.

UMS-0267 Parts list (FM)

The complete list of the required parts and the critical components of the UMS-0267 FM assembly, highlighting important properties and operating temperature ranges.

UMS-0267 Assembly (FM)

Figure 7 shows the 3D render of the CDH FM assembly.

Similar to the CDH EM model, the CDH FM model UMS-0267 consists of 6 layers with the stack up and via configurations, shown in Figure 8. It is followed by layer configurations for each layer.

Conformal Coating Plan

The FM CDH board will be conformally coated with Arathane 5750. The masking diagram for the CDH board is as follows:

Assembly Plan

After the CDH board is built, the subsystem itself can be assembled as follows:

1. Solder the harnessing connecting the CDH and COMMS boards using 4 cables of length 6 cm each (See video here).

Solder at the through-holes at CN3 for the following signals: COMM_PWR_NEG, COMMS_PWR_POS, COMMS_CAN_H and COMMS_CAN_L.

2. Install the COMMS board and CDH board into the COMMS/CDH module (See video here):

a. Install a threaded rod into each of the four corner mounting holes on the COMMS/CDH module.

b. Install the 5/8 inch long spacer onto the threaded rod to separate the COMMS board from the top of the module.

c. Slide in the COMMS board into the module, using the four corner mounting holes on the COMMS board and sliding board into the 4 threaded rods on the module.

d. Install the 7/32 inch long spacer onto the threaded rod to separate the COMMS board from the CDH board.

e. Slide in the CDH board into the module, using the four corner mounting holes on the CDH board and sliding board into the 4 threaded rods on the module.

f. Lock in the CDH and COMMS board into the module using 2-56 hex nuts on each of the 4 threaded rods.

3. Solder the CDH/COMMS data harnessing to the intermodule connector located on the upper surface of the PLD module as follows (See video here):

a. Solder 4 cables of length 6 inch each to the bottom side of the CDH board at location CN3 to account for the following signals: COMM_PWR_NEG, COMMS_PWR_POS, COMMS_CAN_H, and COMMS_CAN_L.

b. Solder 4 cables of length 3 inch each to the bottom side of the CDH board at location CN2 to account for the following signals: JTAG_TCK, JTAG_TDO, JTAG_TMS, and JTAG_TDI.

c. Solder 12 cables of length 6.5 inch each to the bottom side of the CDH board at location CN1 to account for the following signals: CDH_POW_POS, CDH_POW_POS, ADCS_SPI_MOSI, ADCS_SPI_SCK, ADCS_SPI_CS, ADCS_SPI_MISO, CDH_UART_RX, CDH_UART_TX, CDH_CAN_H, CDH_CAN_L, CDH_PWR_NEG, CDH_PWR_NEG.

d. Solder the open end of the 4 cables at CN3, 4 cables at CN2, and 12 cables at CN1 to the appropriate locations on the intermodule connectors located on the upper surface of the PLD module.

4. Flip over the the COMMS/CDH module onto the PLD module to complete the CDH/COMMS assembly.

Pre-Close-Up Verification Activities

Before the module is closed up, two verification activities must be performed:

• Verify that CAN harness is connected.

• Verify that ADCS SPI harness is connected.

• Verify that CDH is mounted properly at its designated place in the structure.