About Mark Gurries

Mark Gurries

San Jose, California

Summary

I am a Hardware Engineer. I have the ability to be a key technical contributor to product design as it relates to system power conversion and management including control.

• Results-oriented and diligent Senior Engineer with a solid record of achievement in analog power and mixed signal design with a recent emphasis on battery-based portable products for consumer and industrial markets.

• Skilled in product design or support as it relates to system power conversion and management including control; able to carry the design from design concept to working boards and beyond, and taking the signals to/from an MCU/FPGA and interface them with the real world.

• Participatory leader with exceptional communication skills and proven record of leading and training technical teams to achieve successful project completion on-time and within budget.

• Respected by colleagues, managers and customers for, attention to detail, strong troubleshooting abilities and commitment to product innovation and customer service excellence.

CORE COMPETENCIES INCLUDE:

Electrical Engineering | Electrical Engineering Team Leadership/ Collaboration

Staff Management & Training | Customer Training | Product Design & Development

Power Design & Management | Customer Support | Application Management

Technical Troubleshooting Patenting/Publishing/ Reporting | Datasheets & Application Notes Development

EMI Compliance | Safety (UL) Compliance | DFT, DFC & DFM design goals

Experience

EPC Efficient Power Conversion

Senior Field Applications Engineer

June 2016 - Present

Field Applications Engineer. Responsible for customer technical support in integrating EPC's GAN FET technology into DC-DC and other switching type topologies. EPC's enhancement mode GAN-FETs is the next generation semiconductor designed to replace traditional Silicon MOSFETs.

Qnovo Inc

Analog & Mixed Signal Product Design Engineer & Applications Manager

May 2011 - June 2016 (5 years 2 months) Newark, Ca

Led hardware design and development of Battery Management Unit (BMU) for notebook and cell phones, incorporating USB, MCU’s, DC-DC & Batrery chargers. Qnovo proprietary battery charging system extendes battery cycle life by 2x or charge batteries faster without increasing damage to the cells.

Selected Achievements & Projects:

• Completed about 37 BMU designs, wrote Qnovo datasheets and application notes for the products and developed two patents.

• Performed HW board development, architecture, schematic design, PCB layout plan and approval using Mentor Graphics PADS and utilized LT-Spice for any required analog circuit simulations. Managed part selection, testing and debug. Given HW spec, returned with working boards to the software development team.

• Designed complete Battery Management Unit boards supporting Gas Gauge, battery protection, JEITA and support for Qnovo advanced charging needs.

• Developed a 5KWhr battery pack system for internal development and an embedded System battery pack design in support of customer applications (Qnovo product integration).

• Assisted with product realization of Qnovo’s proprietary advanced Li-ion charging algorithm development.

• Developed a high current high efficiency battery charging system using paralleling programmable Battery Chargers. Patented

• Developed a control system that charges batteries based on feedback from monitoring circuits. Patended.

Patent Support Electrical Engineer 2011 - 2012 (2 years)

Served as an electrical engineer "Skilled in the Arts" in power supply, power management, memory and mixed signal applications for patents in dispute. Position overlapped work at Qnovo. I worked on the following patents to date:

5,491,774 5,742,737

Linear Technology

Applications Design Engineer and Group Leader

December 1996 - April 2010 (13 years 5 months) Milpitas, Ca

Managed applications support for various power and mixed signal IC products lines with emphasis on Power Management devices including Battery Chargers. Performed product definition, electrical specifications and test/debug of new silicon. Collaborated with members of the IC design team from the start as part of the development process representing applications design and writing these sections for the datasheet. IC's supported included DC-DC, Battery Charger and Power-Path/management control. Some products had digital interfaces such a I2C and SMBus. Primary product focus battery based products (Li-ion, SLA and NiMH). Supported mixed signal parts with complex control functions. Specified PCB layout of the IC's PCB demo-board's.

Selected Achievements & Projects:

• Supervised and mentored several application engineers (both software and hardware) and technicians. Technical training for Field Application Engineers (FAE) on the new parts supported prior to new product introduction.

• Wrote the Data sheet Applications sections. Designed the demonstration PCB boards given to customers for IC evaluation.

• Liaised with all the company's FAEs to assist them with their global customer support needs. Communicated with global customer dispersed around the world to deliver solutions to their design problems.

• Delivered direct technical support to key customers (high volume) including hands-on product debug, integration and design. Implemented process improvements to decrease customer’s technical issues with company IC's.

• Collaborated with IC designers in identifying new product specifications and opportunities.

• Wrote 11+ articles that were published in Linear Magazine, Linear Design Notes, EDN & Electronic Design.

• Represented Linear Technology in the development of the SBS standards: http://smartbattery.org

• Chairman of the Smart Battery System (SBS) Charger Specification committee: http://smartbattery.org/marcom/dc2/14_sbsif_future_course_keynote.pdf

Apple Inc.

Senior Analog Design Engineer

September 1991 - December 1996 (5 years 4 months)

Responsible for all DC-DC, Battery Charger, Power-Path/managment and mixed signal interfacting for the given assigned portable notebook line. Design included EMI compliance and safety aspect as required. Directly worked with PCB designer to implement PCB layout requirements, review/modify layout and give final approval. DC Load complexity ranged from CPU (Core) transient voltage compliance to very low noise sound system supply rails. Defined the power architecture for many product lines that had to support multiple levels of power states. Key aspects of the design was efficient DC- DC operation while only providing power to memory for Standby/Sleep modes of operation. Electrically specified AC Wall adapter requirements. Designs meet high volume DFM, DFT, DFC goals.

Selected Achievements & Projects:

• Implement a new DC to DC architecture for logic power that had the highest efficiency to date for it’s time and who’s high efficiency worked over a 1000:1 current range. Required to implement new “sleep mode” power state that allow instant wake up with no delay.

• Coordinate with multiple vendors to integrate and qualify brand new “state of the art” unreleased parts needed to push notebook design to new levels of size reduction and/or higher efficiency.

• Helped designed an accessory battery charger that can charge two spare external batteries while coordinating/sharing a power a common wall adapter. Patented.

• Helped design the interface between a microcontroller and battery charger to allow programmable voltage control. Patented.

• Designed a method of muting a notebook sound system to prevent audiable noise glitches from the speaker during notebook power cycling or management events. Patented.

• Identified a severe design problem with the very first notebook Li-ion battery pack BMU that were failing in production. Reviewed the designed from the subcontractor and drove the corrective action steps and test.

• Worked on 10 notebook models

Diasonics Ultrasound (GE medical)

Analog Systems Engineer

March 1990 - September 1991 (1 year 7 months) Milpitas, Ca

Ultrasound Imaging Systems. Design multilayer impedance controlled VME computer backplanes that supported mixed signals. Implemented a 1.2KW power factor corrected power supply that met worldwide medical and safety requirements (UL544/IEC601). Evaluated products for EMI compliance in both physical design and testing. Drove product safety compliance to meet UL Safety Standards.

Rugged Digital Systems Inc (Datametrics Corp)

Lead Power System Engineer

September 1987 - March 1990 (2 years 7 months) Sunnyvale, Ca

Military Ruggedized Computer Systems Manufacture. Designed 5W to 1.5KW AC power supplies with the high power versions using DC-DC resonant modules. Designs included power monitoring, fault protection and power control circuits. Everything had to operated over a 0-50C operating range while meeting full Mil-Spec electrical and mechanical standards.

Rolm Mil Spec Computers (Loral)

Manufacturing Analog Test Engineer

April 1984 - September 1987 (3 years 6 months) San Jose, Ca

Mil-Spec Computer Manufacture. Provide analog sustaining support and implement test production tools for production of full Mil-Spec power supplies. Trouble shot down to component level and reviewed with design engineering failure modes and design changes to improve reliability. Design test fixtures to test the various kW level DC input and AC input switching power supplies that had as many as 8 output voltages. Unique power applications were supporting Nuclear EMP pulse applications where the computer had to shutdown fast along with shorting (crow-baring) all supply rails to make the effect of the externally induced current flow from the pulse become common mode to the computer itself. This protects the computer from damage making survivability possible. Involved in support of memory test and debug of modular memory arrays used in the computers. Although DRAM was one of classes of memory, most of the work was involved in Core Memory support which has an intense mixed signal design aspect to it basic operation. (See Schmoo Plots on wikipedia.) Everything has to work over a -55C to a +95C temperature range while passing memory test used to detect bit error defects that show up in the core memory media (medium) itself.

Education

Santa Clara University

BSEE, Electrical Engineering · (1979 - 1984)

Hewlett Packard Corporation EMI design Course by HP 11949A