Verilog DSDによるH-Fi Audioへの挑戦

module audio_clock (

input AUD_MCLK,

input rstn,

output AUD_LRCK,

output AUD_BCLK

);

reg [7:0] lrck_divider;

reg [1:0] bclk_divider;

reg [15:0] shift_out;

wire lrck = !lrck_divider[7];

assign AUD_LRCK = lrck;

assign AUD_BCLK = bclk_divider[1];

always @(posedge AUD_MCLK) begin

if (!rstn) begin

lrck_divider <= 8'hff;

bclk_divider <= 2'b11;

end else begin

lrck_divider <= lrck_divider + 1'b1;

bclk_divider <= bclk_divider + 1'b1;

end

end

endmodule

module i2s_to_lr48(bclk,lrck,din,latch, lr48);

input bclk;

input lrck;

input din;

output [47:0]lr48;

reg [47:0]lr48;

reg [64:0]lr64_tmp;

output latch;

reg latch;

reg [8:0]counter;

reg prv_lrck;

always @ (posedge bclk)

begin

lr64_tmp = lr64_tmp << 1;

lr64_tmp[0] = din;

if (prv_lrck == 1 && lrck == 0)

begin

lr48[47:24] <= lr64_tmp[63:40];

lr48[23:0] <= lr64_tmp[31:8];

latch <= 1;

counter = 0;

end

if (counter == 1)

begin

latch <= 0;

end

counter = counter + 1;

prv_lrck = lrck;

end

endmodule

module lr48_to_dac24lr(latch, lr48,l24,r24);

input latch;

input [47:0]lr48;

output reg [23:0]l24;

output reg [23:0]r24;

always@(negedge latch)

begin

l24 <= lr48[47:24];

r24 <= lr48[23:0];

end

endmodule

module DSD_Mod(Clkin, DAin, DSDout);

input Clkin;

input [23:0] DAin;

output DSDout;

reg [25:0] DSD_accumulator;

always @(posedge Clkin)

begin

DSD_accumulator <= DSD_accumulator[24:0] + (DAin ^ 24'b1000_0000_0000_0000_0000_0000);

end

assign DSDout = DSD_accumulator[25];

endmodule