This is a Module about learning how to learn and use the hardware language Verilog. I'll be posting my lessons, presentations, labs and other resources. This is primarily a Resource Page, so that means it's a Mish-Mash of Silicon Wafer process content.
I'm a huge supporter of Open Source and Creative Commons resources. This is another way of saying Free, Equitable and Accessible resources...
Author: Jim Burnham - TopClown@STEAMClown.org. License: Distributed as Open Source.
Verilog & System Verilog
No explicit prerequisite course work or coding knowledge is required, but students are expected to have a some understanding of basic Math principles.
📰 Slides / 📽️ Video/YouTube / ✨ Resources / 🖼️ Tutorial / 📖 Reading Activity / 📝 Writing Activity / 📖 📝 Reading/Writing / 🛠️ LAB Activity / 🚀 Quiz / 🔎 Review / 🍕 Extra Credit / 🕸️ Web Links
Sid Bar for Teachers: This Module or lesson is how I teach in my class. Many of the lessons might be specific to my class, but you could probably adjust them for your class. I'll try to make them a neutral as I can, so they can be used in any Mathematics, Physics, Computer Science, or any other Engineering / Technology class. Let me know how I can make that better. I'll try to keep this unit current and relevant. Please let me know if any resource links are broken or not accessible. Use this email link to let me know what is broken @ TopClown@STEAMClown.org
I would like to thank <Your Company or Organization Here> for their generous support of my classroom and curriculum development. <Your Company or Organization Here> has <Your value proposition, call to action, & related content and message>
(If you would like to sponsor this presentation, please contact TopClown@STEAMClown.org )
No explicit prerequisite course work or coding knowledge is required, but students are expected to have a good understanding of basic computer principles. Any Digital Logic background is a plus.
Primer: "Aaron, I can imagine no way in which this thing could be considered anywhere remotely close to safe. All I know is I spent six hours in there and I'm still alive... You still want to do it?"
As with any activity, please make sure you are using appropriate safety equipment. If you are coding, writing, reading, or working a lab, make sure you stand up and stretch every hour or so, Please consider any safety issues connecting to a Raspberry Pi, Arduino, computers and other electronic equipment.
What is a VHDL and Verilog?
Verilog
VHDL
System Verilog
VLSI
Chip Design
Check out this short Ubuntu Linux Build Instructions for the Image I use in class.
Here is the Ubuntu Clean Build Shell Script I'm using
wget -O Ubuntu-Clean-Build.sh https://raw.githubusercontent.com/jimTheSTEAMClown/Linux/master/Ubuntu-22-04-2-CleanUpdate.sh
chmod 744 Ubuntu-Clean-Build.sh
./Ubuntu-Clean-Build.sh
These links will be posted later (soon)
Introduction and Links
In this lesson you will get an overview of Verilog language oal of OpenROAD
Lesson Resources:
Verilog Introduction - 📰 Slide Presentation (Planned Spring 2024)
Verilog Introduction - 📖 Lesson Tutorial - (Planned Spring 2024)
Verilog Introduction - 📽️ 🎧Video - (Planned Fall 2023)
Verilog Introduction - LAB #1 - 🛠️ LAB Activity - (Planned Fall 2023)
Verilog Introduction - LAB #2 - 🛠️ LAB Activity - (Planned Fall 2023)
Verilog Introduction - LAB #3 - 🛠️ LAB Activity - (Planned Fall 2023)
In this lesson you are going to learn the steps to create your first Open ROAD project. You will learn the options to execute the following steps:
Install or upgrade a Linux image on a computer or setup a virtual machine
Run the setup scripts (An automated shell setupOpenROAD.sh will be provided to do most of the heavy lifting)
Setup the Visual Studio Code tools
Validate your install is good and completed without errors
Lesson Resources:
Verilog - Tools and Project Installation - 📰 Slide Presentation - (Draft for DAC - July 2023)
Verilog - Tools and Project Installation - 📖 Lesson Tutorial - (Planned Fall 2023)
Verilog - Tools and Project Installation - 📽️ 🎧Video - (Planned Fall 2023)
Verilog - Tools and Project Installation - LAB #1 - 🛠️ LAB Activity - (Planned Fall 2023)
Verilog - Tools and Project Installation - LAB #2 - 🛠️ LAB Activity - (Planned Fall 2023)
Verilog- Tools and Project Installation - LAB #3 - 🛠️ LAB Activity - (Planned Fall 2023)
In this lesson you are going to explore the running of the pre-installed example designs. You will validate the tools and projects are installed correctly and have the ability to run some verification scripts on a default build of the GCD (Greatest Common Divisor) design. You will learn the steps to create your first Open ROAD Design. Explore / Review the following project features:
Directory locations for pre-built source files
Directory, Module and File naming conventions
Config and Constraint parameters and settings
Running the make flow
Validating your design process correctly
Lesson Resources:
Verilog - Pre-Built Project Introduction Exploration - 📰 Slide Presentation - (Draft for DAC - July 2023)
Verilog - Pre-Built Project Introduction Exploration - 📖 Lesson Tutorial - (Planned Fall 2023)
Verilog - Pre-Built Project Introduction Exploration - 📽️ 🎧Video - (Planned Fall 2023)
Verilog - Pre-Built Project Introduction Exploration - LAB #1 - 🛠️ LAB Activity - (Planned Fall 2023)
Verilog - Pre-Built Project Introduction Exploration - LAB #2 - 🛠️ LAB Activity - (Planned Fall 2023)
Verilog - Pre-Built Project Introduction Exploration - LAB #3 - 🛠️ LAB Activity - (Planned Fall 2023)
In this lesson you are going to explore the creation of your first Verilog OpenROAD Project. You will learn the steps to create your first Open ROAD Design. Explore / Review the following project features:
Directory locations for Verilog source files
Directory, Module and File naming conventions
Config and Constraint parameters and settings
Running the make flow
Validating your design process correctly
Lesson Resources:
Verilog - Building A New Verilog Counter Design - 📰 Slide Presentation - (Draft for DAC - July 2023)
Verilog - Building A New Verilog Counter Design - 📖 Lesson Tutorial - (Planned Fall 2023)
Verilog - Building A New Verilog Counter Design - 📽️ 🎧Video - (Planned Fall 2023)
Verilog - Building A New Verilog Counter Design - LAB #1 - 🛠️ LAB Activity - (Planned Fall 2023)
Verilog - Building A New Verilog Counter Design - LAB #2 - 🛠️ LAB Activity - (Planned Fall 2023)
Verilog - Building A New Verilog Counter Design - LAB #3 - 🛠️ LAB Activity - (Planned Fall 2023)
Digital Logic - Verilog - Visual Studio Code Project Introduction Exploration - 📰 Slide Presentation (Coming Soon - Placeholder Link)
Digital Logic - Verilog - Visual Studio Code Project Introduction Exploration - 📖 Lesson Tutorial
Digital Logic - Verilog - Visual Studio Code Project Introduction Exploration - 📽️ 🎧Video
Digital Logic - Verilog - Visual Studio Code Project Introduction Exploration - LAB #1 - 🛠️ LAB Activity
Digital Logic - Verilog - Visual Studio Code Project Introduction Exploration - LAB #2 - 🛠️ LAB Activity
Digital Logic - Verilog - Visual Studio Code Project Introduction Exploration - LAB #3 - 🛠️ LAB Activity
Verilog - Verilog Synthesis Flow - 📰 Slide Presentation (Coming Soon - Placeholder Link)
Verilog - Verilog Synthesis Flow - 📖 Lesson Tutorial
Verilog - Verilog Synthesis Flow - 📽️ 🎧Video
Verilog - Verilog Synthesis Flow - LAB #1 - 🛠️ LAB Activity
Verilog - Verilog Synthesis Flow - LAB #2 - 🛠️ LAB Activity
Verilog - Verilog Synthesis Flow - LAB #3 - 🛠️ LAB Activity
Lecture and Lab Topics:
The-OpenROAD-Project Intro
OpenROAD RTL-GDSII simulation and verification flow
Building blocks of open-source design (this should introduce .libs. .v source and public pdks briefly if not covered in the previous module covering RTL-GDSII)
Running the OpenROAD flow from RTL-GDSII (key stages and intermediate results briefly)
Key advantages and features of OpenROAD flow
OpenROAD GUI Introduction
Validating the design for Tapeout - My First Chip Labs - 4-5 labs that incorporate the following steps, to complete a design ready for submission
Lab #1 - Initial tools and flow for placement setup
Initialize floorplan - define the chip size and cell rows
Place pins (for designs without pads )
Lab #2 - Using Macros and other Structures
Place macro cells (RAMs, embedded macros)
Insert substrate tap cells
Insert power distribution network
Macro Placement of macro cells
Global placement of standard cells
Lab #3 - Checking and Adjusting Timing and Placement
Repair max slew, max capacitance, and max fanout violations and long wires
Clock tree synthesis
Optimize setup/hold timing
Lab #4 - Finishing Touches
Insert fill cells
Global routing (route guides for detailed routing)
Antenna repair
Detailed routing
Parasitic extraction
Lab #5 - Final Analysis
Static timing analysis
Contributing to the open-source design community using the OpenROAD ecosystem
Each lecture and lab modules will contain the following collateral and curriculum so that a STEAM teacher anywhere in a Highschool or Community College can implement the course work.
Modules deliverables will include: (about 4 hours of 30 min Lectures & 8+ hours of Lab & Assessment activities)
Google Docs: 📰 Slide Presentation / 🖼️ Lesson Tutorial / ✨ Resources
Canvas LMS Module: 🛠️ LAB Activities and 🚀 Formative & Summative Assessments
https://science.xyz/news/launching-science-foundry - work on getting high school flow.
Digital Logic - Introduction to the OpenROAD Project: This Module will cover the OpenROAD flows and Scripts
Modules deliverables will include: (about 4 hours of 30 min Lectures & 8+ hours of Lab & Assessment activities)
Google Docs: 📰 Slide Presentation / 🖼️ Lesson Tutorial / ✨ Resources
Canvas LMS Module: 🛠️ LAB Activities and 🚀 Formative & Summative Assessments
Notes: This is a comment from @dralabeing that I need to follow up on, where to add some more timing analysis: Timing analysis is generally done at different stages- first time pre-layout after CTS, post-global-routing, after detailed routing and chip finishing. So this topic can be introduce sooner.
Links & Resources:
Topics:
The-OpenROAD-Project Intro
OpenROAD RTL-GDSII simulation and verification flow
Building blocks of open-source design (this should introduce .libs. .v source and public pdks briefly if not covered in the previous module covering RTL-GDSII)
Running the OpenROAD flow from RTL-GDSII (key stages and intermediate results briefly)
Key advantages and features of OpenROAD flow
OpenROAD GUI Introduction
Validating the design for Tapeout - My First Chip Labs - 4-5 labs that incorporate the following steps, to complete a design ready for submission
Lab #1 - Initial tools and flow for placement setup
Initialize floorplan - define the chip size and cell rows
Place pins (for designs without pads )
Lab #2 - Using Macros and other Structures
Place macro cells (RAMs, embedded macros)
Insert substrate tap cells
Insert power distribution network
Macro Placement of macro cells
Global placement of standard cells
Lab #3 - Checking and Adjusting Timing and Placement
Repair max slew, max capacitance, and max fanout violations and long wires
Clock tree synthesis
Optimize setup/hold timing
Lab #4 - Finishing Touches
Insert fill cells
Global routing (route guides for detailed routing)
Antenna repair
Detailed routing
Parasitic extraction
Lab #5 - Final Analysis
Static timing analysis
Contributing to the open-source design community using the OpenROAD ecosystem
Links that will help us build this project:
Here is the outline I was thinking of: 3 hr lecture- 3 hr labs
1. Define what is meant by RTL 2 GDSII in general for ASIC applications.
A lecture to show the basics of a typical ASIC Design flow. You can explain this in the context of OpenROAD as well.
Also introduce the building blocks such as libraries, PDKS, rules, constraints etc briefly.
I have attached a set of slides based on our current presentation--this may be too complex but it gives you an idea of the flow. The design images can be substituted by a simpler example like GCD. (Github-> https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/tree/master/flow/designs/sky130hd/gcd)
2. Show the RTL- GDS flow in OpenROAD-flow-scripts
Explain briefly input/outputs at each stage and handoffs of the flow and the associated functional role.
e.g a Systems architect - designs the system given the components with a targeted design goal for power, performance, area
RTL engineer- Defines the register transfer level based on the architecture and synthesizes a netlist (Verilog, VHDL etc.) . We support Verilog.
3. Introduction to physical design - basic concepts of standard cell placement , creation of a power grid, i/o pins to connect to the external world,
goals - reducing wirelength
4. Some basic analysis like timing, area utilization, density etc. using the OpenROAD GUI.
5. Final chip handoff- importance of ensuring that this design can be made manufacturable based on skywater 130nm or GF180 pdk.
Lab demo - GCD (greatest common divisor) from ORFS Github-> https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/tree/master/flow/designs/sky130hd/gcd
I can help set you up with ORFS and share a simple demo example.
Student project- Pick any design from the ORFS design repo, choose a design goal and improve that (area, utiization, timing etc)
Extra credit- Student selects any open source design core and completes the flow in ORFS.
- Submit a GitHub issue (problem found) or a fix via a PR from the ORFS set of issues to contribute. This may be a huge stretch goal but students inclined towards software, scripts, document improvements can contribute.
Here's a MEMS foundry that was recently launched recently--something that could be very useful for your class.
https://science.xyz/news/launching-science-foundry
Here's the latest infor on Tiny Tapeout: https://www.youtube.com/watch?v=fblSVCPvCiY
We should include a plan for student projects on Tiny Tapeout.
NSF Link to teacher Education research grant opportunities
This Lesson is coming soon - click here to be notified when it's available - Professional Development Newsletter
Mechatronics - <topic> - 📖 Lesson Tutorial
Mechatronics - <topic> - 📽️ Video / 🎧 Podcast
Mechatronics - <topic> - 📰 Slide Presentation (Coming Soon)
Mechatronics - <topic> - LAB #1 - 🛠️ LAB Activity
Mechatronics - <topic> - LAB #2 - 🛠️ LAB Activity
Mechatronics - <topic> - LAB #3 - 🛠️ LAB Activity
If you are a teacher and want to connect and teach this Lesson or Module, discuss how I teach it, give me feedback, please contact me at TopClown@STEAMClown.org
To access this Lesson Plan and the Teacher collaboration area, you will have needed to connect with me so I can Share the content with you. Please go to the Teachers & Partner Page, check out my Licensing and fill out my Collaboration and Curriculum Request Form. I'll review and then grant you access to the requested areas and lesson plans if they exist.
If you have questions or feedback on how I can make a presentation, lesson, lab better please give use my Feedback Form.
I’ll work on getting these in, but it’s the last thing I want to work on :-) When I have them updated, I’ll move to the top of the Lesson Plan.
NGSS: <list standard numbers>
California CTE Standards: <list standard numbers>
Related Instructional Objectives (SWBAT): <list standard numbers>
CCSS: nnn, RSIT: nnn, RLST: nnn, WS: nnn, WHSST: nnn, A-CED: nnn, ETS: nnn <list standard numbers>
Main Standard:
Priority standards:
National Standards:
Reference Text Book - Basic College Mathematics with Early Integers 4th edition - Elayn Martin-Gay - University of New Orleans - Pearson
Reference Sites -
https://imgbin.com/png/ZJtzkYZZ/under-construction-png
