4:1 MUX

AIM: Simulate, synthesize & implement the following combinational  and sequential designs using Structural description:

Multiplexer(4:1) using top down approach

4:1 MUX

Verilog code:

module mux4_1tda(y,sel,i);

output y;

input [3:0]i;

input[1:0]sel;

mux2_1 mux1(mux1_out,sel[0],i[0],i[1]);

mux2_1 mux2(mux2_out,sel[0],i[2],i[3]);

mux2_1 mux3(y,sel[1],mux1_out,mux2_out);

endmodule

module mux2_1(y,sel,i0,i1);

output y;

input i0,i1,sel;

wire w1,w2,w3;

not g1(w1,sel);

and g2(w2,w1,i0);

and g3(w3,sel,i1);

or g4(y,w2,w3);

endmodule

Test bench code:

module tb_mux4_1tda();

wire y;

reg [3:0]i;

reg[1:0]sel;

mux4_1tda DUT (y,sel,i);

initial begin

i=4'b0101; #10;

 sel=2'b00; #10;

 sel=2'b01;#10;

 sel=2'b10;#10;

 sel=2'b11;#10;

#20 $finish;

end

endmodule

module tb_mux2_1;

wire y;

reg i0,i1,sel;

mux2_1 DUT (y,sel,i0,i1);

initial begin

i0=1'b1;i1=1'b0;sel=1'b0;#10;

i0=1'b1;i1=1'b0;sel=1'b1;#10;

#20 $finish;

end

endmodule

OUTPUT: