THEORY 

A synchronous counter is a digital counting circuit in which all flip-flops are triggered by the same common clock signal. Because every stage changes state simultaneously on each clock pulse, the counter operates faster and avoids the ripple delay seen in asynchronous counters. The next state of each flip-flop is determined by combinational logic that examines the present state, allowing the counter to produce a smooth, predictable sequence such as up-counting, down-counting, or modulo-N counting. This uniform clocking makes synchronous counters reliable and suitable for high-speed digital systems

Block diagram

WAVEFORM:

VERILOG CODE 

module tb_syn_up_cnt();

wire [3:0]q;

reg clk,reset;

syn_up_cnt dux(q,clk,reset);

initial begin

clk=0;

repeat(20)

#5 clk=~clk;

end

initial begin 

reset=1;

#20 reset =0;

#500 reset=1;

end 

endmodule

TEST BENCH 

module tb_syn_up_cnt();

wire [3:0]q;

reg clk,reset;

syn_up_cnt dux(q,clk,reset);

initial begin

clk=0;

repeat(20)

#5 clk=~clk;

end

initial begin 

reset=1;

#20 reset =0;

#500 reset=1;

end 

endmodule

OUTPUT:

RTL SCHEMATIC:

POWER:

TIME

UTILIZATION REPORT