Embedded Files
Verilog Code:-
module xs3_to_bcd (
input X3, X2, X1, X0,
output B3, B2, B1, B0
);
assign B3 = X3 & (X2 | X1);
assign B2 = (~X2 & X1) | (X2 & ~X1);
assign B1 = (~X2 & X0) | (X1 & X0) | (~X1 & X2 & ~X0);
assign B0 = ~X0;
endmodule
Test Bench:
module tb_xs3_to_bcd;
reg X3, X2, X1, X0;
wire B3, B2, B1, B0;
xs3_to_bcd dut (X3, X2, X1, X0, B3, B2, B1, B0);
initial
begin
X3=0; X2=0; X1=1; X0=1; #10;
X3=0; X2=1; X1=0; X0=0; #10;
X3=0; X2=1; X1=0; X0=1; #10;
X3=0; X2=1; X1=1; X0=0; #10;
X3=0; X2=1; X1=1; X0=1; #10;
X3=1; X2=0; X1=0; X0=0; #10;
X3=1; X2=0; X1=0; X0=1; #10;
X3=1; X2=0; X1=1; X0=0; #10;
X3=1; X2=0; X1=1; X0=1; #10;
X3=1; X2=1; X1=0; X0=0; #10;
end
endmodule
OUTPUT:
Pin Assignment:-
> Input = J15
> Input = L16
> Input = M13
> Input=R15
> Output = H17
> Output = K15
> Output=J13
> Output=N14
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