16 BIT RCA

AIM: Simulate, synthesize & implement the following combinational  and sequential designs using Structural description:

16-bit RCA using top down approach

Verilog code:

module struct_full_A(a, b, cin, sum, cout);

  input a, b, cin;

  output sum, cout;

  wire w1, w2, w3;

  xor G1 (w1, a, b);

  xor G2 (sum, w1, cin);

  and G3 (w2, w1, cin);

  and G4 (w3, a, b);

  or  G5 (cout, w2, w3);

endmodule

// 16-bit Ripple Carry Adder

module rca_16bit(sum, cout, a, b, cin);

  input [15:0] a, b;

  input cin;

  output cout;

  output [15:0] sum;

  wire [15:0] c;

  // Instantiate 16 full adders

  struct_full_A fa_0 (a[0],  b[0],  cin,   sum[0],  c[0]);

  struct_full_A fa_1 (a[1],  b[1],  c[0],  sum[1],  c[1]);

  struct_full_A fa_2 (a[2],  b[2],  c[1],  sum[2],  c[2]);

  struct_full_A fa_3 (a[3],  b[3],  c[2],  sum[3],  c[3]);

  struct_full_A fa_4 (a[4],  b[4],  c[3],  sum[4],  c[4]);

  struct_full_A fa_5 (a[5],  b[5],  c[4],  sum[5],  c[5]);

  struct_full_A fa_6 (a[6],  b[6],  c[5],  sum[6],  c[6]);

  struct_full_A fa_7 (a[7],  b[7],  c[6],  sum[7],  c[7]);

  struct_full_A fa_8 (a[8],  b[8],  c[7],  sum[8],  c[8]);

  struct_full_A fa_9 (a[9],  b[9],  c[8],  sum[9],  c[9]);

  struct_full_A fa_10(a[10], b[10], c[9],  sum[10], c[10]);

  struct_full_A fa_11(a[11], b[11], c[10], sum[11], c[11]);

  struct_full_A fa_12(a[12], b[12], c[11], sum[12], c[12]);

  struct_full_A fa_13(a[13], b[13], c[12], sum[13], c[13]);

  struct_full_A fa_14(a[14], b[14], c[13], sum[14], c[14]);

  struct_full_A fa_15(a[15], b[15], c[14], sum[15], c[15]);

  // Final carry-out

  assign cout = c[15];

endmodule

Test bench code:

module tb_rca_16bit();

reg [15:0] a, b;

reg cin;

wire [15:0] sum;

rca_16bit DUT(sum, cout, a, b, cin);

initial begin

 a=16'b0000000000000001;b=16'b0000000000000001;cin=0;

#10 a=16'b1111111111111111;b=16'b0000000000000001;cin=0;

#10 a=16'b0000000000000001;b=16'b0000000000000001;cin=1;

$finish();

end 

endmodule

OUTPUT: