AND GATE :

Theory :

An AND gate is a basic digital logic gate that implements logical multiplication.

1.It has two or more inputs and one output.

2.The output is HIGH (1) only when all inputs are HIGH (1).

3.If any input is LOW (0), the output becomes LOW (0)

BLOCK DIAGRAM:

Boolean expression :     Y=A⋅B 

Verilog Code :

                
module AND2_1(Y,A,B);

input A,B;

output Y;

assign Y = (A&B);

endmodule

Test bench :

         module tb_AND2_1();

                reg A,B;

wire Y;

AND2_1 DUX(Y,A,B);

initial 

begin 

    A=1'b0 ; B=1'b0;

    #10 A=1'b0 ; B=1'b1;

    #10 A=1'b1 ; B=1'b0;

    #10 A=1'b1 ; B=1'b1;

    #20 $finish();

    end 

endmodule

OUTPUT:

 Pin Assignment: 

Input A = J15

Input B = L16

Output Y = H17