CIRCUIT DIAGRAM:

BLOCK DIAGRAM:

TRUTHTABLE:

WAVEFROM:

VERILOG CODE 

module jkff(q,qb,j,k,clk);

input j,k,clk;

output q,qb;

reg q=0;

reg qb=1;

always @(posedge clk)

begin

    if (j==0 && k==0)

        q=q;

    else if (j==0 && k==1)

        q=0;

    else if (j==1 && k==0)

        q=1;

    else

        q=~q;

    qb <= ~q;

end

endmodule

TESTBENCH 

module tb_jkff();

wire q,qb;

reg j,k,clk;

jkff dux(q,qb,j,k,clk);

initial

begin

clk = 0;

repeat(10)

begin

    #5 clk =~clk;

end

end

initial

begin

j = 0; k = 0;

#10 j = 1; k = 0;

#10 j = 0; k = 1;

#10 j = 1; k = 1;

#20 $finish;

end

endmodule

RTL SCHEMATIC:

POWER:

TIME:

UTILAZATION REPORT:

OUTPUT: