16:1 MUX

AIM: Simulate, synthesize & implement the following combinational  and sequential designs using Structural description:

Multiplexer(16:1) using top down approach

Verilog code:

module mux16_1tda(y,sel,i);

output y;

input [15:0]i;

input [3:0]sel;

wire mux1_out,mux2_out,mux3_out,mux4_out;

mux4_1 mux1(mux1_out,sel[1:0],i[3:0]);

mux4_1 mux2(mux2_out,sel[1:0],i[7:4]);

mux4_1 mux3(mux3_out,sel[1:0],i[11:8]);

mux4_1 mux4(mux4_out,sel[1:0],i[15:12]);

mux4_1 mux5(y, sel[3:2], {mux4_out, mux3_out, mux2_out, mux1_out});

endmodule

module mux4_1(y,sel,i);

output y;

input [3:0]i; 

input [1:0]sel;

wire w1,w2,w3,w4,w5,w6;

not g1(w1,sel[0]);

not g2(w2,sel[1]);

and g3(w3,w1,w2,i[0]);

and g4(w4,sel[1],w2,i[1]);

and g5(w5,sel[1],w1,i[2]);

and g6(w6,sel[1],sel[0],i[3]);

or g7(y,w3,w4,w5,w6);

endmodule

Test bench code:

module tb_mux16_1tda();

reg  [15:0] i;

reg  [3:0]  sel;

wire y;

mux16_1tda DUT (y,sel,i);

initial begin

    i   = 16'b0101010101010101;  

    sel = 4'b0000;#10

    sel = 4'b0001;#10

    sel = 4'b0010;#10

    sel = 4'b0011;#10

    sel = 4'b0100;#10;

    sel = 4'b0101;#10;

    sel = 4'b0110;#10;

    sel = 4'b0111;#10;

    sel = 4'b1000;#10;

    #10 $finish;

end

endmodule

OTPUT: