VERILOG CODE 

module decoder_2_4(y,I);

input [1:0]I;

output reg [3:0]y;

always @(I)

begin

case(I)

2'd0 : y=4'd1;

2'd1 : y=4'd2;

2'd2 : y=4'd4;

2'd3 : y=4'd8;

endcase 

end 

endmodule

TEST BENCH 

module tb_decoder_2_4();

wire [3:0]y;

reg [1:0]I;

decoder_2_4 dut(y,I);

initial 

begin 

I=2'd0 ;

#10 I=2'd1 ; 

#10 I=2'd2 ; 

#10 I=2'd3 ; 

#20 $finish;

end

endmodule

RTL SCHEMATIC:

POWER

TIMING REPORT:

UTILIZATION REPORT: